MC9S08SV16CLC

Freescale Semiconductor Document NumberDocument Number: MC9S08SV16: MC9S08SV16 ReRevv.. 2, 7/2009 2, 7/2009 Data Sheet: Technical Data MC9S08SV16 MC9S08SV16 Series 32-Pin SDIP 32-Pin LQFP Covers: MC9S08SV16 and 1376-02 873A-03 MC9S08SV8 Features: On-chip in-circuit emulator (ICE) debug module containing two comparators and nine trigger modes 8-Bit HCS08 Central Processor Unit (CPU) Peripherals Up to 40 MHz CPU at 2.7 V to 5.5 V across temperature IPC Interrupt priority controller to provide hardware range of 40 C to 85 C based nested interrupt mechanism HC08 instruction set with added BGND instruction ADC 12-channel, 10-bit resolution 2.5 s Support for up to 32 interrupt/reset sources conversion time automatic compare function On-Chip Memory 1.7 mV/C temperature sensor internal bandgap Up to 16 KB flash read/program/erase over full reference channel operation in stop optional hardware operating voltage and temperature trigger fully functional from 2.7 V to 5.5 V Up to 1024-byte random-access memory (RAM) TPM One 6-channel and one 2-channel Security circuitry to prevent unauthorized access to timer/pulse-width modulators (TPM) modules RAM and flash contents selectable input capture, output compare, or buffered Power-Saving Modes edge- or center-aligned PWM on each channel Two low power stop modes reduced power wait mode MTIM16 One 16-bit modulo timer Allows clocks to remain enabled to specific peripherals SCI One serial communications interface module in stop3 mode with optional 13-bit break LIN extensions Clock Source Options SPI One serial peripheral interface module in 8-bit Oscillator (XOSC) Loop-control Pierce oscillator data length mode with a receiving data buffer hardware crystal or ceramic resonator range of 31.25 kHz to match function 39.0625 kHz or 1 MHz to 16 MHz IIC Inter-integrated circuit bus module capable of Internal Clock Source (ICS) Internal clock source operation up to 100 kbps with maximum bus loading module containing a frequency-locked-loop (FLL) multi-master operation programmable slave address controlled by internal or external reference precision interrupt-driven byte-by-byte data transfer broadcast trimming of internal reference allows 0.2% resolution mode 10-bit addressing and 2% deviation over temperature and voltage ACMP Analog comparator with option to compare to supporting bus frequencies up to 20 MHz internal reference System Protection RTC Real time counter Watchdog computer operating properly (COP) reset KBI 8-pin keyboard interrupt module with software with option to run from dedicated 1 kHz internal clock selectable polarity on edge or edge/level modes source or bus clock Input/Output Low-voltage detection with reset or interrupt selectable 30 GPIOs including one output-only pin and one trip points input-only pin Illegal opcode detection with reset Package Options Illegal address detection with reset 32-pin SDIP Flash block protection 32-pin LQFP Development Support Single-wire background debug interface Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints) This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. Freescale Semiconductor, Inc., 2009. All rights reserved.Table of Contents 1 MCU Block Diagram . 3 5.9.1 Control Timing . 23 2 System Clock Distribution . 4 5.9.2 TPM Module Timing . 24 3 Pin Assignments 5 5.9.3 SPI Timing 25 4 Memory Map . 8 5.10 Analog Comparator (ACMP) Electricals . 27 5 Electrical Characteristics 9 5.11 ADC Characteristics 28 5.1 Introduction 9 5.12 Flash Specifications 30 5.2 Parameter Classification 9 5.13 EMC Performance . 31 5.3 Absolute Maximum Ratings . 9 5.13.1Radiated Emissions . 31 5.4 Thermal Characteristics . 10 6 Ordering Information 32 5.5 ESD Protection and Latch-Up Immunity . 11 7 Package Information 33 5.6 DC Characteristics . 12 7.1 Mechanical Drawings . 33 5.7 Supply Current Characteristics 18 5.8 External Oscillator (XOSC) and ICS Characteristics 21 5.9 AC Characteristics . 23 Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: