MC33689DPEW

Document Number: MC33689 Freescale Semiconductor Rev. 8.0, 9/2012 Technical Data System Basis Chip with LIN 33689D Transceiver The 33689 is a serial peripheral interface (SPI) controlled system basis chip (SBC) that combines many frequently used functions in an MCU-based system plus a local interconnect network (LIN) SYSTEM BASIS CHIP WITH LIN transceiver. Applications include power window, mirror, and seat controls. The 33689 has a 5.0 V, 50 mA low dropout regulator with full protection and reporting features. The device provides full SPI- readable diagnostics and a selectable timing watchdog for detecting errant operation. The LIN transceiver waveshaping circuitry can be disabled for higher data rates. One 50 mA and two 150 mA high side switches with output protection are available to drive inductive or resistive loads. The 150 mA switches can be pulse-width modulated (PWM). Two high voltage inputs are available for contact monitoring or as external wake-up inputs. A current sense operational amplifier is EW SUFFIX (PB-FREE) available for load current monitoring. 98ARH99137A 32-PIN SOICW The 33689 has three operational modes: Normal (all functions available) Sleep (VDD OFF, wake-up via LIN bus or wake-up inputs) Stop (VDD ON, wake-up via MCU, LIN bus, or wake-up inputs) ORDERING INFORMATION Device Features Temperature (Add R2 Suffix for Tape Package Range (T ) Full-duplex SPI Interface at frequencies up to 4.0 MHz A and Reel) LIN transceiver capable to 100 kbps with waveshaping capability MC33689DPEW -40 C to 125 C 32 SOICW 5.0 V low dropout regulator with full fault detection and protection One 50 mA and two 150 mA protected high side switches Current sense operational amplifier Compatible with LIN 2.0 specification package V V DD PWR 33689 VS1 HS3 VS2 L1 VCC 5.0 V L2 VDD WDC HS1 CS CS HS2 SCK SCLK MCU SPI MOSI MOSI MISO MISO E+ INT E- RST GND IN TGND OUT AGND TXD LIN BUS RXD Figure 1. 33689 Simplified Application Diagram Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. Freescale Semiconductor, Inc., 2006-2012. All rights reserved.INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM 5.0 V/50 mA VS1 VDD Voltage Regulator Reset RST Control Window VS2 WDC Watchdog IN HS1 MOSI SPI HS2 MISO and SCLK Mode Pre-Driver CS Control HS3 INT VCC L1 Current E- Sense E+ L2 Op Amp OUT VS1 TXD LIN LIN Physical Interface RXD GND TGND AGND Figure 2. 33689 Simplified Internal Block Diagram 33689 Analog Integrated Circuit Device Data 2 Freescale Semiconductor