LS1088AXE7Q1A

Document Number LS1088A NXP Semiconductors Rev. 1, 02/2019 Data Sheet: Technical Data LS1088A QorIQ LS1088A Data Sheet Features Eight SerDes lanes for high-speed peripheral interfaces: LS1088A contains eight ARM Cortex-A53 (32/64 Three PCI Express 3.0 controllers (one supporting bit) cores with the following capabilities: x4 operation) Speed up to 1.6 GHz One serial ATA (SATA 3.0) controller supporting Arranged as two clusters of four cores 6 Gbps 32 KB L1 instruction cache (ECC protection) and 32 Up to two SGMII supporting 2500 Mbps KB L1 data cache (ECC protection) Up to four SGMII supporting 1000 Mbps Two 1 MB unified I/D L2 cache (ECC protection), Up to two XFI (10 GbE) interfaces one per Cortex-A53 core cluster Up to two QSGMII NEON SIMD coprocessor Supports 1000Base-KX ARMv8 cryptography extensions Supports 10GBase-KR Hierarchical interconnect fabric: Additional peripheral interfaces include: Hardware-managed data coherency One quad serial peripheral interface (QSPI) Up to 700 MHz operation controller, one serial peripheral interface (SPI) One 32/64-bit DDR4 SDRAM memory controller: controller ECC and interleaving support Integrated flash controller (IFC) supporting NAND Up to 2.1 GT/s and NOR flash with 28-bit addressing and 16-bit data Datapath acceleration architecture 2.0 (DPAA2) Two USB 3.0 controllers with integrated PHY incorporates acceleration for the following functions: Enhanced secure digital host controller supporting Packet parsing, classification, and distribution SD 3.0, eMMC 4.4, and eMMC 4.5 modes (WRIOP) uQE supporting TDM/HDLC Queue management for scheduling, packet Four I2C controllers sequencing, and congestion management (QMan) Two 16550-compliant DUARTs Hardware buffer management for buffer allocation General purpose IO (GPIO), four FlexTimers, and and de-allocation (BMan) nine watchdog timers Cryptography acceleration (SEC) Trust architecture IEEE 1588 support Debug support with run control, data acquisition, Advanced I/O processor (AIOP) high-speed trace, and performance/event monitoring Parallel Ethernet interfaces: 780 FC-PBGA package, 23 mm x 23 mm, 0.8 mm Up to two RGMII interfaces pitch NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.Table of Contents 1 Overview.............................................................................................. 3 3.17 I2C interface.............................................................................. 145 2 Pin assignments.................................................................................... 3 3.18 Integrated Flash Controller........................................................148 2.1 780 BGA ball layout diagrams..................................................3 3.19 JTAG interface.......................................................................... 167 2.2 Pinout list...................................................................................10 3.20 Quad serial peripheral interface (QuadSPI).............................. 170 3 Electrical characteristics.......................................................................51 3.21 QUICC engine specifications....................................................174 3.1 Overall DC electrical characteristics.........................................51 3.22 Serial peripheral interface (SPI)................................................ 180 3.2 General AC timing specifications............................................. 58 3.23 Universal serial bus (USB) interface.........................................185 3.3 Power sequencing......................................................................59 4 Hardware design considerations...........................................................188 3.4 Power-down requirements.........................................................62 4.1 Clock ranges.............................................................................. 188 3.5 Power characteristics.................................................................62 4.2 Power supply design..................................................................189 3.6 Power-on ramp rate................................................................... 64 5 Thermal................................................................................................ 190 3.7 Input clocks............................................................................... 64 5.1 Recommended thermal model...................................................191 3.8 RESET initialization timing specifications............................... 70 5.2 Temperature diode.....................................................................191 3.9 Battery-backed security monitor interface................................ 71 5.3 Thermal management information............................................ 191 3.10 DDR4 SDRAM controller.........................................................73 6 Package information.............................................................................194 3.11 Dual universal asynchronous receiver/transmitter (DUART) 6.1 Package parameters for the FC-PBGA......................................194 interface..................................................................................... 78 6.2 Mechanical dimensions of the FC-PBGA................................. 194 3.12 Enhanced secure digital host controller (eSDHC).....................80 7 Security fuse processor.........................................................................196 3.13 Ethernet interface (EMI, RGMII, and IEEE Std 1588).............88 8 Ordering information............................................................................196 3.14 General purpose input/output (GPIO) interface........................ 98 8.1 Part numbering nomenclature....................................................196 3.15 Generic interrupt controller (GIC) interface..............................102 8.2 Part marking ............................................................................. 197 3.16 High-speed serial interfaces (HSSI).......................................... 104 9 Revision history....................................................................................198 QorIQ LS1088A Data Sheet, Rev. 1, 02/2019 2 NXP Semiconductors