LS1012AXE7HKB

Enterprise-class security and packet acceleration in a 1 W typical power microprocessor QorIQ Layerscape LS1012A Communications Processor The Layerscape LS1012A processor provides intelligent integration and extreme power efficiency in a small 9.6 x 9.6 mm package for fanless, small form factor networking and IoT applications. TARGET APPLICATIONS caches and incorporates the same trust architecture and software compatibility of higher-tier Layerscape family devices. Trust-enabled IoT gateways The LS1012A processor features 32 KB of L1 instruction and Consumer NAS data cache and 256 KB of coherent L2 cache. In addition, Mobile NAS (battery powered) the Cortex-A53 core features the NEON SimD module and dual-precision floating point unit (FPU). The memory controller Ethernet drives for data center center storage supports 16-bit DDR3L memory devices at 1 GHz. Entry-level broadband Ethernet gateways SYSTEM INTERFACES AND NETWORKING Building and factory automation The LS1012A processor features a three-lane, 6 GHz multi- Incorporating a 64-bit Arm Cortex -A53 core, the LS1012A protocol SerDes that provides support for high-speed processor delivers CoreMark performance of over 4,000 interfaces, including up to two Gigabit Ethernet ports, as well as hardware acceleration for packet processing and DMA-controlled PCI Express generation 2.0 port, and one security, and the best overall performance of any 1 W typical SATA 3.0 port. The LS1012A processor also features dual power communications processor. USB controllersone supporting SuperSpeed USB 3.0 with integrated PHY, the other supporting USB 2.0 functions. CORE COMPLEX Additional interfaces include QuadSPI and support for The LS1012A processor integrates a single Arm Cortex-A53 SD/MMC. core running up to 1 GHz with ECC-protected L1 and L2 The LS1012A includes a hardware LS1012A BLOCK DIAGRAM packet forwarding engine (PFE) which Arm offloads processing of IP packets Cortex -A53 from the main CPU, yielding higher 32 KB 32 KB L1-D L1-I performance and lower power than 16-bit DDR3L 128 KB Memory SRAM 256 KB L2 pure software processing can achieve. Controller QorIQ Trust Architecture The PFE is capable of 2 Gbit/s IP Secure Boot Arm TrustZone CoreLink CCI-400 Coherent Interconnect forwarding even with the smallest Security Monitor packets, with virtually no CPU load. Security Power Management Packet Forwarding Engine 2 x SD 3.0/SDIO/eMMC Engine COMPLETE ENABLEMENT, 2 2 x I C RICH ECOSYSTEM 2 5 x I S QSPI, 1 x SPI For customer evaluation, the LS1012A 2 x UART processor is supported by an evaluation 3-Lane 6 GHz SERDES GPIO, JTAG board featuring an integrated on-board 1 x USB 3.0 + PHY probe for further cost savings, along with 1 x USB 2.0 third-party platforms developed by NXPs Core Complex Basic Peripherals and Interconnect Accelerators and Memory Control Networking Elements embedded board solution partners. Evaluation kits include a Linux BSP with optimized drivers to support peripherals LS1012A FEATURES and a six-month evaluation license for Extreme power efficiency, delivering over 4,000 CoreMarks 64-bit Arm Cortex -A53 core CodeWarrior development tools. For at 1 W typical power quick product prototyping, NXP offers First 1 W typical power embedded processor featuring Arm ECC-protected cache memories Cortex-A53 core with ECC protected caches and coherent the FRYW-LS1012A board with a built- 256 KB L2 for high reliability applications in mikroBUS Click Module that opens Rich connectivity and peripheral High integration that enables support for 802.11ac modules the door to easy expansion through features including PCI Express Gen2, and high bandwidth connectivity for ASICs, 4G/LTE, SATA, hundreds of powerful click modules USB 3.0, SATA 3, QuadSPI, SDIO low-cost NOR Flash supporting sensors, actuators, memories Delivers hardware acceleration for outstanding IP forwarding Packet acceleration engine and NAS performance and displays. Support for Arm TrustZone and secure boot, together All LS series devices are supported by Security and trust architecture with high performance cryptographic processing and manufacturing protection our Product Longevity Program to ensure The LS1012A package is engineered to support low-cost, a stable supply of products, as well as Low-cost board designs 4-layer board designs to minimize system costs our extensive third-party ecosystem, the largest and most established in the communications market. In conjunction with our expertise and worldwide support infrastructure, the ecosystem helps customers accelerate their migration from both competitive solutions and from legacy NXP devices, preserve investment costs and reduce time-to-market. www.nxp.com/QorIQ NXP, the NXP logo, Freescale, CodeWarrior, Layerscape, QorIQ and SMARTMOS, are trademarks of NXP B.V. Document Number: All other product or service names are the property of their respective owners. ARM, Cortex and TrustZone are LS1012AFS REV 0 registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. CoreLink and NEON are trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. 2018 NXP B.V. GbE GbE PCIe 2.0 SATA 3.0