FS32R274KSK2MMM

Document Number S32R274 NXP Semiconductors Rev. 6, 06/2021 Data Sheet: Technical Data S32R274 S32R274/S32R264 Series Data Sheet Supports S32R274K, S32R274J, S32R264K and S32R264J Features Functional Safety Enables up to ASIL-D applications On-chip modules available within the device include FCCU for fault collection and fault handling the following features: MEMU for memory error management Safety core: Power Architecture e200Z4 32-bit CPU Safe eDMA controller with checker core Self-Test Control Unit (STCU2) Error Injection Module (EIM) Dual issue computation cores: Power Architecture On-chip voltage monitoring e200Z7 32-bit CPU Clock Monitor Unit (CMU) 2 MB on-chip code flash (FMC flash) with ECC Security 1.5 MB on-chip SRAM with ECC Cryptographic Security Engine (CSE2) Supports censorship and life-cycle management RADAR processing Signal Processing Toolbox (SPT) for RADAR signal Timers processing acceleration Two Periodic Interval Timers (PIT) with 32-bit Cross Timing Engine (CTE) for precise timing counter resolution generation and triggering Three System Timer Module (STM) Waveform generation module (WGM) for chirp Three Software Watchdog Timers (SWT) ramp generation Two eTimer modules with 6 channels each 4x 12-bit -ADC with 10 MSps One FlexPWM module for 12 PWM signals One DAC with 10 MSps Communication Interfaces MIPICSI2 interface to connect external ADCs Two Serial Peripheral interface (SPI) modules Memory Protection One LINFlexD module Each core memory protection unit provides 24 Two inter-IC communication interface (I2C) entries modules Data and instruction bus system memory protection One dual-channel FlexRay module with 128 unit (SMPU) with 16 region descriptors each message buffers Register protection Three FlexCAN modules with configurable buffers - CAN FD optionally supported on 2 FlexCAN Clock Generation modules 40 MHz external crystal (XOSC) One ENET MAC supporting MII/RMII/RGMII 16 MHz Internal oscillator (IRCOSC) interface Dual system PLL with one frequency modulated ZipWire high-speed serial communication phase-locked loop (FMPLL) Low-jitter PLL to -ADC and DAC clock Debug Functionality generation (not supported on SC66760x devices) 4-pin JTAG interface and Nexus/Aurora interface for serial high-speed tracing e200Z7 core and e200Z4 core: Nexus development interface (NDI) per IEEE-ISTO 5001-2012 Class 3+ NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. Two analog-to-digital converters (SAR ADC) Each ADC supports up to 16 input channels Cross Trigger Unit (CTU) On-chip voltage DC/DC regulator for core clock (VREG) Two Temperature Sensors (TSENS) S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021 2 NXP Semiconductors