Product Information

74LVC373APW,118

Hot 74LVC373APW,118 electronic component of Nexperia

Datasheet
Latches OCTAL TRANSP LATCH

Manufacturer: Nexperia
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1250: USD 0.0969 ea
Line Total: USD 121.12

1387 - Global Stock
Ships to you between
Tue. 30 Apr to Fri. 03 May
MOQ: 1250  Multiples: 1
Pack Size: 1
Availability Price Quantity
1387 - Global Stock


Ships to you between
Tue. 30 Apr to Fri. 03 May

MOQ : 1250
Multiples : 1
1250 : USD 0.0969

2081 - Global Stock


Ships to you between Mon. 29 Apr to Wed. 01 May

MOQ : 1
Multiples : 1
1 : USD 0.4278
10 : USD 0.3312
100 : USD 0.2473
500 : USD 0.2162
1000 : USD 0.1794
2500 : USD 0.1506
10000 : USD 0.1472

7275 - Global Stock


Ships to you between Tue. 23 Apr to Mon. 29 Apr

MOQ : 2500
Multiples : 2500
2500 : USD 0.1544

7527 - Global Stock


Ships to you between Tue. 23 Apr to Mon. 29 Apr

MOQ : 51
Multiples : 1
51 : USD 0.173
100 : USD 0.1707
250 : USD 0.1684
500 : USD 0.1661
1000 : USD 0.1627

472 - Global Stock


Ships to you between Tue. 23 Apr to Mon. 29 Apr

MOQ : 71
Multiples : 1
71 : USD 0.1012

     
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74LVC373A Octal D-type transparent latch with 5 V tolerant inputs/outputs 3-state Rev. 5 27 August 2021 Product data sheet 1. General description The 74LVC373A is an octal D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using I . The I circuitry OFF OFF disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits Overvoltage tolerant inputs to 5.5 V Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Direct interface with TTL levels High-impedance outputs when V = 0 V CC I circuitry provides partial Power-down mode operation OFF Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from -40 C to +85 C and -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC373AD -40 C to +125 C SO20 plastic small outline package 20 leads SOT163-1 body width 7.5 mm 74LVC373APW -40 C to +125 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mm 74LVC373ABQ -40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal enhanced SOT764-1 very thin quad flat package no leads 20 terminals body 2.5 4.5 0.85 mmNexperia 74LVC373A Octal D-type transparent latch with 5 V tolerant inputs/outputs 3-state 4. Functional diagram 1 EN 11 D7 Q7 18 19 C1 D6 Q6 17 16 3 2 1D D5 Q5 14 15 4 5 D4 Q4 13 12 7 6 D3 Q3 8 9 8 9 D2 Q2 7 6 13 12 D1 Q1 4 5 14 15 D0 Q0 3 2 17 16 LE OE 18 19 mna881 11 1 mna880 Fig. 1. Logic symbol Fig. 2. IEC logic symbol D0 Q0 3 2 D1 Q1 4 5 D2 Q2 7 6 D3 Q3 8 9 LATCH 3-STATE D4 Q4 13 1 to 8 OUTPUTS 12 LE D5 Q5 14 15 D6 Q6 17 16 D7 Q7 18 19 LE LE 11 LE D Q 1 OE mna189 mna882 LE Fig. 3. Functional diagram Fig. 4. Logic diagram (one latch) D0 D1 D2 D3 D4 D5 D6 D7 D Q D Q D Q D Q D Q D Q D Q D Q LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 mna883 Fig. 5. Logic diagram 74LVC373A All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 5 27 August 2021 2 / 15

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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