74LVC30APWJ

74LVC30A 8-input NAND gate Rev. 2 15 March 2019 Product data sheet 1. General description The 74LVC30A is an 8-input NAND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices in a mixed 3.3 V and 5 V environment. Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall time. This device is fully specified for partial power-down applications using I . The I circuitry OFF OFF disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features and benefits Wide supply voltage range from 1.2 V to 3.6 V Inputs accept voltages up to 5.5 V CMOS low power consumption Direct interface with TTL levels Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JEDEC JS-001-2012 exceeds 2000 V MM JESD22-A115-C exceeds 200 V CDM JESD22-C101F exceeds 1000 V Specified from -40 C to +85 C and -40 C to +125 CNexperia 74LVC30A 8-input NAND gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC30AD -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74LVC30APW -40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74LVC30ABQ -40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1 very thin quad flat package no leads 14 terminals body 2.5 x 3 x 0.85 mm 4. Functional diagram 1 A 1 & 2 B 2 3 C 3 4 D 4 Y 8 8 5 E 5 6 F 6 11 G 11 12 H 12 mna488 mna489 Fig. 1. Logic symbol Fig. 2. IEC logic symbol A B C D Y E mna490 F G H Fig. 3. Logic diagram 74LVC30A All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2019. All rights reserved Product data sheet Rev. 2 15 March 2019 2 / 13