74LVC2G32DC-Q100H

74LVC2G32-Q100 Dual 2-input OR gate Rev. 2 14 December 2016 Product data sheet 1. General description The 74LVC2G32-Q100 provides a 2-input OR gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using I . The I OFF OFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant outputs in the Power-down mode High noise immunity 24 mA output drive (V =3.0 V) CC CMOS low power consumption Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )74LVC2G32-Q100 Nexperia Dual 2-input OR gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC2G32DP-Q100 40 C to +125 C TSSOP8 plastic thin shrink small outline package 8 leads SOT505-2 body width 3 mm lead length 0.5 mm 74LVC2G32DC-Q100 40 C to +125 C VSSOP8 plastic very thin shrink small outline package SOT765-1 8 leads body width 2.3 mm 4. Marking Table 2. Marking codes 1 Type number Marking code 74LVC2G32DP-Q100 V32 74LVC2G32DC-Q100 V32 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram < K DD Fig 1. Logic symbol Fig 2. IEC logic symbol % < PQ Fig 3. Logic diagram (one gate) 74LVC2G32 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 2 14 December 2016 2 of 14 D DDK % < %