74LVC2G125GN

74LVC2G125 Dual bus buffer/line driver 3-state Rev. 14 29 March 2013 Product data sheet 1. General description The 74LVC2G125 provides a dual non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (pin nOE). A HIGH-level at pin nOE causes the output to assume a high-impedance OFF-state. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using I . The I OFF OFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. 2. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant input/output for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V 24 mA output drive (V = 3.0 V) CC CMOS low-power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V Multiple package options Specified from 40 C to +85 C and 40 C to +125 C74LVC2G125 NXP Semiconductors Dual bus buffer/line driver 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC2G125DP 40 Cto+125 C TSSOP8 plastic thin shrink small outline package 8 leads SOT505-2 body width 3 mm lead length 0.5 mm 74LVC2G125DC 40 Cto+125 C VSSOP8 plastic very thin shrink small outline package 8 leads SOT765-1 body width 2.3 mm 74LVC2G125GT 40 Cto+125 C XSON8 plastic extremely thin small outline package no leads SOT833-1 8 terminals body 1 1.95 0.5 mm 74LVC2G125GF 40 C to +125 C XSON8 extremely thin small outline package no leads SOT1089 8 terminals body 1.35 1 0.5 mm 74LVC2G125GD 40 Cto+125 C XSON8 plastic extremely thin small outline package no leads SOT996-2 8 terminals body 3 2 0.5 mm 74LVC2G125GM 40 C to +125 C XQFN8 plastic, extremely thin quad flat package no leads SOT902-2 8 terminals body 1.6 1.6 0.5 mm 74LVC2G125GN 40 C to +125 C XSON8 extremely thin small outline package no leads SOT1116 8 terminals body 1.2 1.0 0.35 mm 74LVC2G125GS 40 C to +125 C XSON8 extremely thin small outline package no leads SOT1203 8 terminals body 1.35 1.0 0.35 mm 4. Marking Table 2. Marking codes 1 Type number Marking code 74LVC2G125DP V25 74LVC2G125DC V25 74LVC2G125GT V25 74LVC2G125GF VM 74LVC2G125GD V25 74LVC2G125GM V25 74LVC2G125GN VM 74LVC2G125GS VM 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 74LVC2G125 All information provided in this document is subject to legal disclaimers. NXP B.V. 2013. All rights reserved. Product data sheet Rev. 14 29 March 2013 2 of 22