74LVC1T45GW

74LVC1T45 74LVCH1T45 Dual supply translating transceiver 3-state Rev. 6 6 August 2012 Product data sheet 1. General description The 74LVC1T45 74LVCH1T45 are single bit, dual supply transceivers with 3-state outputs that enable bidirectional level translation. They feature two 1-bit input-output ports (A and B), a direction control input (DIR) and dual supply pins (V and V ). Both CC(A) CC(B) V and V can be supplied at any voltage between 1.2 V and 5.5 V making the CC(A) CC(B) device suitable for translating between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins A and DIR are referenced to V and pin B is referenced CC(A) to V . A HIGH on DIR allows transmission from A to B and a LOW on DIR allows CC(B) transmission from B to A. The devices are fully specified for partial power-down applications using I . The I OFF OFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either V or V are at CC(A) CC(B) GND level, both A port and B port are in the high-impedance OFF-state. Active bus hold circuitry in the 74LVCH1T45 holds unused or floating data inputs at a valid logic level. 2. Features and benefits Wide supply voltage range: V : 1.2 V to 5.5 V CC(A) V : 1.2 V to 5.5 V CC(B) High noise immunity Complies with JEDEC standards: JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8C (2.7 V to 3.6 V) JESD36 (4.5 V to 5.5 V) ESD protection: HBM JESD22-A114F Class 3A exceeds 4000 V CDM JESD22-C101E exceeds 1000 V Maximum data rates: 420 Mbps (3.3 V to 5.0 V translation) 210 Mbps (translate to 3.3 V)) 140 Mbps (translate to 2.5 V) 75 Mbps (translate to 1.8 V) 60 Mbps (translate to 1.5 V) Suspend mode74LVC1T45 74LVCH1T45 NXP Semiconductors Dual supply translating transceiver 3-state Latch-up performance exceeds 100 mA per JESD 78 Class II 24 mA output drive (V =3.0 V) CC Inputs accept voltages up to 5.5 V Low power consumption: 16 A maximum I CC I circuitry provides partial Power-down mode operation OFF Multiple package options Specified from 40 Cto+85 C and 40 Cto+125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC1T45GW 40 Cto +125 C SC-88 plastic surface-mounted package 6 leads SOT363 74LVCH1T45GW 74LVC1T45GM 40 Cto +125 C XSON6 plastic extremely thin small outline package no leads SOT886 6 terminals body 1 1.45 0.5 mm 74LVCH1T45GM 74LVC1T45GF 40 C to +125 C XSON6 plastic extremely thin small outline package no leads SOT891 6 terminals body 1 1 0.5 mm 74LVCH1T45GF 74LVC1T45GN 40 C to +125 C XSON6 extremely thin small outline package no leads SOT1115 6 terminals body 0.9 1.0 0.35 mm 74LVCH1T45GN 74LVC1T45GS 40 C to +125 C XSON6 extremely thin small outline package no leads SOT1202 6 terminals body 1.0 1.0 0.35 mm 74LVCH1T45GS 4. Marking Table 2. Marking 1 Type number Marking code 74LVC1T45GW V5 74LVCH1T45GW X5 74LVC1T45GM V5 74LVCH1T45GM X5 74LVC1T45GF V5 74LVCH1T45GF X5 74LVC1T45GN V5 74LVCH1T45GN X5 74LVC1T45GS V5 74LVCH1T45GS X5 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 74LVC LVCH1T45 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 6 August 2012 2 of 33