74LVC138APW-Q100J

74LVC138A-Q100 3-to-8 line decoder/demultiplexer inverting Rev. 3 28 August 2020 Product data sheet 1. General description The 74LVC138A-Q100 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The 74LVC138A features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the 74LVC138A-Q100 to a 1-of-32 (5 to 32 lines) decoder with just four 74LVC138A-Q100 ICs and one inverter. The 74LVC138A-Q100 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Overvoltage tolerant inputs to 5.5 V Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Direct interface with TTL levels Demultiplexing capability Multiple input enable for easy expansion Ideal for memory chip select decoding Mutually exclusive outputs Output drive capability 50 transmission lines at 125 C Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package options DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder jointsNexperia 74LVC138A-Q100 3-to-8 line decoder/demultiplexer inverting 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC138AD-Q100 -40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74LVC138APW-Q100 -40 C to +125 C TSSOP16 plastic thin shrink small outline package SOT403-1 16 leads body width 4.4 mm 74LVC138ABQ-Q100 -40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal SOT763-1 enhanced very thin quad flat package no leads 16 terminals body 2.5 3.5 0.85 mm 4. Functional diagram DX 15 X/Y 15 0 0 1 14 1 14 0 1 1 1 2 0 13 2 13 G 2 Y0 2 2 1 A0 15 7 3 12 3 12 2 A1 Y1 14 2 3 4 3 11 11 3 A2 13 Y2 4 4 12 Y3 10 10 4 4 & & 5 5 E1 Y4 11 9 9 4 5 5 6 6 Y5 10 E2 EN 5 7 7 6 6 9 7 7 Y6 E3 6 7 Y7 mna371 (a) (b) mna370 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Y0 15 A0 Y1 1 14 2 A1 Y2 13 3 A2 Y3 12 3-to-8 ENABLE Y4 11 DECODER EXITING Y5 10 Y6 9 7 Y7 4 E1 5 E2 6 E3 mna372 Fig. 3. Functional diagram 74LVC138A Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 3 28 August 2020 2 / 14