74LVC02APW

74LVC02A Quad 2-input NOR gate Rev. 8 16 November 2011 Product data sheet 1. General description The 74LVC02A provides four 2-input NOR gates. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications. 2. Features and benefits 5 V tolerant inputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Direct interface with TTL levels Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from 40 Cto+85 C and 40 Cto+125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC02AD 40 Cto +125 C SO14 plastic small outline package; 14 leads; SOT108-1 body width 3.9 mm 74LVC02ADB 40 Cto +125 C SSOP14 plastic shrink small outline package; 14 leads; SOT337-1 body width 5.3 mm 74LVC02APW 40 Cto +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; SOT402-1 body width 4.4 mm 74LVC02ABQ 40 Cto +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package; no leads; 14 terminals; body 2.5 3 0.85 mm74LVC02A NXP Semiconductors Quad 2-input NOR gate 4. Functional diagram 2 1 1 3 2 1A 1Y 1 3 1B 5 1 4 5 2A 6 2Y 4 A 6 2B 8 Y 3A 3Y 10 8 1 9 3B 10 B 9 mna215 11 4A 4Y 13 12 4B 11 1 13 mna216 12 mna217 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram for one gate 5. Pinning information 5.1 Pinning terminal 1 index area 2 13 1A 4Y 1B 3 12 4B 1Y 1 14 V CC 2Y 4 02 11 4A 1A 2 13 4Y 1B 3 12 4B 2A 5 (1) 10 3Y GND 2Y 4 02 11 4A 2B 6 9 3B 2A 5 10 3Y 2B 6 9 3B 001aac920 GND 7 8 3A 001aac919 Transparent top view (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 4. Pin configuration SO14 and (T)SSOP14 Fig 5. Pin configuration DHVQFN14 74LVC02A All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 8 16 November 2011 2 of 14 GND 7 1 1Y 3A 8 14 V CC