74HCT4051PW,118

74HC4051 74HCT4051 8-channel analog multiplexer/demultiplexer Rev. 10 8 September 2021 Product data sheet 1. General description The 74HC4051 74HCT4051 is a single-pole octal-throw analog switch (SP8T) suitable for use in analog or digital 8:1 multiplexer/demultiplexer applications. The switch features three digital select inputs (S0, S1 and S2), eight independent inputs/outputs (Yn), a common input/output (Z) and a digital enable input (E). When E is HIGH, the switches are turned off. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Wide analog input voltage range from -5 V to +5 V CMOS low power dissipation High noise immunity Complies with JEDEC standards JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Low ON resistance: 80 (typical) at V - V = 4.5 V CC EE 70 (typical) at V - V = 6.0 V CC EE 60 (typical) at V - V = 9.0 V CC EE Logic level translation: to enable 5 V logic to communicate with 5 V analog signals Typical break before make built-in ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Multiple package options Specified from -40 C to +85 C and -40 C to +125 C 3. Applications Analog multiplexing and demultiplexing Digital multiplexing and demultiplexing Signal gatingNexperia 74HC4051 74HCT4051 8-channel analog multiplexer/demultiplexer 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC4051D -40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74HCT4051D 74HC4051PW -40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 74HCT4051PW 74HC4051BQ -40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1 very thin quad flat package no leads 16 terminals 74HCT4051BQ body 2.5 3.5 0.85 mm 5. Functional diagram V CC 16 13 Y0 S0 11 14 Y1 15 Y2 S1 10 12 Y3 LOGIC 1 Y4 1-OF-8 LEVEL DECODER CONVERSION S2 9 5 Y5 2 Y6 E 6 4 Y7 3 Z 8 7 GND V 001aad543 EE Fig. 1. Functional diagram 74HC HCT4051 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 10 8 September 2021 2 / 27