74HCT280N

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT280 9-bit odd/even parity generator/checker December 1990 Product specication File under Integrated Circuits, IC06Philips Semiconductors Product specication 9-bit odd/even parity generator/checker 74HC/HCT280 FEATURES transmission or data retrieval systems. Both even and odd parity outputs are available for generating or checking Word-length easily expanded by cascading even or odd parity up to 9 bits. Similar pin configuration to the 180 for easy system The even parity output ( ) is HIGH when an even number E up-grading of data inputs (I to I ) are HIGH. The odd parity output ( ) 0 8 0 Generates either odd or even parity for nine data bits is HIGH when an odd number of data inputs are HIGH. Output capability: standard Expansion to larger word sizes is accomplished by tying I category: MSI CC the even outputs ( ) of up to nine parallel devices to the E data inputs of the final stage. For a single-chip 16-bit even/odd parity generator/checker, see GENERAL DESCRIPTION PC74HC/HCT7080. The 74HC/HCT280 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL APPLICATIONS (LSTTL). They are specified in compliance with JEDEC standard no. 7A. 25-line parity generator/checker The 74HC/HCT280 are 9-bit parity generators or checkers 81-line parity generator/checker commonly used to detect errors in high-speed data QUICK REFERENCE DATA GND = 0 V; T =25C; t =t = 6 ns amb r f TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC HCT t / t propagation delay C = 15 pF; V =5 V PHL PLH L CC I to 17 18 ns n E I to 20 22 ns n O C input capacitance 3.5 3.5 pF I C power dissipationcapacitance per package notes 1 and 2 65 65 pF PD Notes 1. C is used to determine the dynamic power dissipation (P in W): PD D 2 2 P =C V f + (C V f ) where: D PD CC i L CC o f = input frequency in MHz i f = output frequency in MHz o 2 (C V f ) = sum of outputs L CC o C = output load capacitance in pF L V = supply voltage in V CC 2. For HC the condition is V = GND to V I CC For HCT the condition is V = GND to V - 1.5 V I CC ORDERING INFORMATION See 74HC/HCT/HCU/HCMOS Logic Package Information. December 1990 2