Product Information

74HCT174D.652

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IC: digital; D flip-flop; Channels:6; HCT; SMD; SO16; Package: tube
Manufacturer: NXP


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Manufacturer
NXP
Product Category
Flip-Flops
Kind Of Integrated Circuit
D Flip-Flop
Case
So16
Mounting
Smd
Trigger
Positive-Edge-Triggered
Kind Of Package
TUBE
Type Of Integrated Circuit
Digital
Series
Hct
Number Of Channels
6
Operating Temperature
- 40 To 125 C
Supply Voltage
4.5 To 5.5 VDC
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74HC174; 74HCT174 Hex D-type flip-flop with reset; positive-edge trigger Rev. 3 ? 16 April 2013 Product data sheet 1. General description The 74HC174; 74HCT174 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output. A LOW on MR causes the flip-flops and outputs to be reset LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits ? Input levels: ? For 74HC174: CMOS level ? For 74HCT174: TTL level ? Six edge-triggered D-type flip-flops ? Asynchronous master reset ? Complies with JEDEC standard no. 7A ? ESD protection: ? HBM JESD22-A114F exceeds 2000 V ? MM JESD22-A115-A exceeds 200 V. ? Multiple package options ? Specified from ?40 ?C to +85 ?C and ?40 ?C to +125 ?C. 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC174N ?40 ?C to +125 ?C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 74HCT174N 74HC174D ?40 ?C to +125 ?C SO16 plastic small outline package; 16 leads; body width SOT109-1 3.9 mm 74HCT174D 74HC174DB ?40 ?C to +125 ?C SSOP16 plastic shrink small outline package; 16 leads; SOT338-1 body width 5.3 mm 74HCT174DB 74HC174PW ?40 ?C to +125 ?C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm 74HCT174PW 74HC174; 74HCT174 Hex D-type flip-flop with reset; positive-edge trigger Rev. 3 ? 16 April 2013 Product data sheet 1. General description The 74HC174; 74HCT174 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output. A LOW on MR causes the flip-flops and outputs to be reset LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits ? Input levels: ? For 74HC174: CMOS level ? For 74HCT174: TTL level ? Six edge-triggered D-type flip-flops ? Asynchronous master reset ? Complies with JEDEC standard no. 7A ? ESD protection: ? HBM JESD22-A114F exceeds 2000 V ? MM JESD22-A115-A exceeds 200 V. ? Multiple package options ? Specified from ?40 ?C to +85 ?C and ?40 ?C to +125 ?C. 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC174N ?40 ?C to +125 ?C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 74HCT174N 74HC174D ?40 ?C to +125 ?C SO16 plastic small outline package; 16 leads; body width SOT109-1 3.9 mm 74HCT174D 74HC174DB ?40 ?C to +125 ?C SSOP16 plastic shrink small outline package; 16 leads; SOT338-1 body width 5.3 mm 74HCT174DB 74HC174PW ?40 ?C to +125 ?C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm 74HCT174PW74HC174; 74HCT174 NXP Semiconductors Hex D-type flip-flop with reset; positive-edge trigger 4. Functional diagram                                           Fig 1. Logic symbol Fig 2. IEC logic symbol                                Fig 3. Logic diagram 74HC_HCT174 All information provided in this document is subject to legal disclaimers. ? NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3 ? 16 April 2013 2 of 18 74HC174; 74HCT174 Hex D-type flip-flop with reset; positive-edge trigger Rev. 3 ? 16 April 2013 Product data sheet 1. General description The 74HC174; 74HCT174 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output. A LOW on MR causes the flip-flops and outputs to be reset LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits ? Input levels: ? For 74HC174: CMOS level ? For 74HCT174: TTL level ? Six edge-triggered D-type flip-flops ? Asynchronous master reset ? Complies with JEDEC standard no. 7A ? ESD protection: ? HBM JESD22-A114F exceeds 2000 V ? MM JESD22-A115-A exceeds 200 V. ? Multiple package options ? Specified from ?40 ?C to +85 ?C and ?40 ?C to +125 ?C. 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC174N ?40 ?C to +125 ?C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 74HCT174N 74HC174D ?40 ?C to +125 ?C SO16 plastic small outline package; 16 leads; body width SOT109-1 3.9 mm 74HCT174D 74HC174DB ?40 ?C to +125 ?C SSOP16 plastic shrink small outline package; 16 leads; SOT338-1 body width 5.3 mm 74HCT174DB 74HC174PW ?40 ?C to +125 ?C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm 74HCT174PW 74HC174; 74HCT174 Hex D-type flip-flop with reset; positive-edge trigger Rev. 3 ? 16 April 2013 Product data sheet 1. General description The 74HC174; 74HCT174 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output. A LOW on MR causes the flip-flops and outputs to be reset LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits ? Input levels: ? For 74HC174: CMOS level ? For 74HCT174: TTL level ? Six edge-triggered D-type flip-flops ? Asynchronous master reset ? Complies with JEDEC standard no. 7A ? ESD protection: ? HBM JESD22-A114F exceeds 2000 V ? MM JESD22-A115-A exceeds 200 V. ? Multiple package options ? Specified from ?40 ?C to +85 ?C and ?40 ?C to +125 ?C. 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC174N ?40 ?C to +125 ?C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 74HCT174N 74HC174D ?40 ?C to +125 ?C SO16 plastic small outline package; 16 leads; body width SOT109-1 3.9 mm 74HCT174D 74HC174DB ?40 ?C to +125 ?C SSOP16 plastic shrink small outline package; 16 leads; SOT338-1 body width 5.3 mm 74HCT174DB 74HC174PW ?40 ?C to +125 ?C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm 74HCT174PW74HC174; 74HCT174 NXP Semiconductors Hex D-type flip-flop with reset; positive-edge trigger 4. Functional diagram                                           Fig 1. Logic symbol Fig 2. IEC logic symbol                                Fig 3. Logic diagram 74HC_HCT174 All information provided in this document is subject to legal disclaimers. ? NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3 ? 16 April 2013 2 of 1874HC174; 74HCT174 NXP Semiconductors Hex D-type flip-flop with reset; positive-edge trigger 5. Pinning information 5.1 Pinning                                                                                                 Fig 4. Pin configuration DIP16 Fig 5. Pin configuration SO16 Fig 6. Pin configuration SSOP16 and TSSOP16 5.2 Pin description Table 2. Pin description Symbol Pin Description MR 1 asynchronous master reset input (active LOW) Q0 to Q5 2, 5, 7, 10, 12, 15 flip-flop output D0 to D5 3, 4, 6, 11, 13, 14 data input GND 8 ground (0 V) CP 9 clock input (LOW-to-HIGH edge-triggered) V 16 positive supply voltage CC 74HC_HCT174 All information provided in this document is subject to legal disclaimers. ? NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3 ? 16 April 2013 3 of 18 74HC174; 74HCT174 Hex D-type flip-flop with reset; positive-edge trigger Rev. 3 ? 16 April 2013 Product data sheet 1. General description The 74HC174; 74HCT174 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output. A LOW on MR causes the flip-flops and outputs to be reset LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits ? Input levels: ? For 74HC174: CMOS level ? For 74HCT174: TTL level ? Six edge-triggered D-type flip-flops ? Asynchronous master reset ? Complies with JEDEC standard no. 7A ? ESD protection: ? HBM JESD22-A114F exceeds 2000 V ? MM JESD22-A115-A exceeds 200 V. ? Multiple package options ? Specified from ?40 ?C to +85 ?C and ?40 ?C to +125 ?C. 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC174N ?40 ?C to +125 ?C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 74HCT174N 74HC174D ?40 ?C to +125 ?C SO16 plastic small outline package; 16 leads; body width SOT109-1 3.9 mm 74HCT174D 74HC174DB ?40 ?C to +125 ?C SSOP16 plastic shrink small outline package; 16 leads; SOT338-1 body width 5.3 mm 74HCT174DB 74HC174PW ?40 ?C to +125 ?C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm 74HCT174PW 74HC174; 74HCT174 Hex D-type flip-flop with reset; positive-edge trigger Rev. 3 ? 16 April 2013 Product data sheet 1. General description The 74HC174; 74HCT174 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output. A LOW on MR causes the flip-flops and outputs to be reset LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits ? Input levels: ? For 74HC174: CMOS level ? For 74HCT174: TTL level ? Six edge-triggered D-type flip-flops ? Asynchronous master reset ? Complies with JEDEC standard no. 7A ? ESD protection: ? HBM JESD22-A114F exceeds 2000 V ? MM JESD22-A115-A exceeds 200 V. ? Multiple package options ? Specified from ?40 ?C to +85 ?C and ?40 ?C to +125 ?C. 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC174N ?40 ?C to +125 ?C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 74HCT174N 74HC174D ?40 ?C to +125 ?C SO16 plastic small outline package; 16 leads; body width SOT109-1 3.9 mm 74HCT174D 74HC174DB ?40 ?C to +125 ?C SSOP16 plastic shrink small outline package; 16 leads; SOT338-1 body width 5.3 mm 74HCT174DB 74HC174PW ?40 ?C to +125 ?C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm 74HCT174PW74HC174; 74HCT174 NXP Semiconductors Hex D-type flip-flop with reset; positive-edge trigger 4. Functional diagram                                           Fig 1. Logic symbol Fig 2. IEC logic symbol                                Fig 3. Logic diagram 74HC_HCT174 All information provided in this document is subject to legal disclaimers. ? NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3 ? 16 April 2013 2 of 18 74HC174; 74HCT174 Hex D-type flip-flop with reset; positive-edge trigger Rev. 3 ? 16 April 2013 Product data sheet 1. General description The 74HC174; 74HCT174 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output. A LOW on MR causes the flip-flops and outputs to be reset LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits ? Input levels: ? For 74HC174: CMOS level ? For 74HCT174: TTL level ? Six edge-triggered D-type flip-flops ? Asynchronous master reset ? Complies with JEDEC standard no. 7A ? ESD protection: ? HBM JESD22-A114F exceeds 2000 V ? MM JESD22-A115-A exceeds 200 V. ? Multiple package options ? Specified from ?40 ?C to +85 ?C and ?40 ?C to +125 ?C. 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC174N ?40 ?C to +125 ?C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 74HCT174N 74HC174D ?40 ?C to +125 ?C SO16 plastic small outline package; 16 leads; body width SOT109-1 3.9 mm 74HCT174D 74HC174DB ?40 ?C to +125 ?C SSOP16 plastic shrink small outline package; 16 leads; SOT338-1 body width 5.3 mm 74HCT174DB 74HC174PW ?40 ?C to +125 ?C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm 74HCT174PW 74HC174; 74HCT174 Hex D-type flip-flop with reset; positive-edge trigger Rev. 3 ? 16 April 2013 Product data sheet 1. General description The 74HC174; 74HCT174 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output. A LOW on MR causes the flip-flops and outputs to be reset LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits ? Input levels: ? For 74HC174: CMOS level ? For 74HCT174: TTL level ? Six edge-triggered D-type flip-flops ? Asynchronous master reset ? Complies with JEDEC standard no. 7A ? ESD protection: ? HBM JESD22-A114F exceeds 2000 V ? MM JESD22-A115-A exceeds 200 V. ? Multiple package options ? Specified from ?40 ?C to +85 ?C and ?40 ?C to +125 ?C. 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC174N ?40 ?C to +125 ?C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 74HCT174N 74HC174D ?40 ?C to +125 ?C SO16 plastic small outline package; 16 leads; body width SOT109-1 3.9 mm 74HCT174D 74HC174DB ?40 ?C to +125 ?C SSOP16 plastic shrink small outline package; 16 leads; SOT338-1 body width 5.3 mm 74HCT174DB 74HC174PW ?40 ?C to +125 ?C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm 74HCT174PW74HC174; 74HCT174 NXP Semiconductors Hex D-type flip-flop with reset; positive-edge trigger 4. Functional diagram                                           Fig 1. Logic symbol Fig 2. IEC logic symbol                                Fig 3. Logic diagram 74HC_HCT174 All information provided in this document is subject to legal disclaimers. ? NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3 ? 16 April 2013 2 of 1874HC174; 74HCT174 NXP Semiconductors Hex D-type flip-flop with reset; positive-edge trigger 5. Pinning information 5.1 Pinning                                                                                                 Fig 4. Pin configuration DIP16 Fig 5. Pin configuration SO16 Fig 6. Pin configuration SSOP16 and TSSOP16 5.2 Pin description Table 2. Pin description Symbol Pin Description MR 1 asynchronous master reset input (active LOW) Q0 to Q5 2, 5, 7, 10, 12, 15 flip-flop output D0 to D5 3, 4, 6, 11, 13, 14 data input GND 8 ground (0 V) CP 9 clock input (LOW-to-HIGH edge-triggered) V 16 positive supply voltage CC 74HC_HCT174 All information provided in this document is subject to legal disclaimers. ? NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3 ? 16 April 2013 3 of 18

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