74HC7541PW-Q100J

74HC7541-Q100 74HCT7541-Q100 Octal Schmitt trigger buffer/line driver 3-state Rev. 2 3 August 2021 Product data sheet 1. General description The 74HC7541-Q100 74HCT7541-Q100 is an 8-bit buffer/line driver with Schmitt-trigger inputs and 3-state outputs. The device features two output enables (OE1 and OE2). A HIGH on OEn causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of V . CC Schmitt trigger inputs transform slowly changing input signals into sharply defined jitter-free output signals. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range from 2.0 to 6.0 V CMOS low power dissipation High noise immunity Unlimited input rise and fall times Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) Non-inverting outputs Input levels: For 74HC7541-Q100: CMOS level For 74HCT7541-Q100: TTL level ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC7541D-Q100 -40 C to +125 C SO20 plastic small outline package 20 leads SOT163-1 body width 7.5 mm 74HCT7541D-Q100 74HC7541PW-Q100 -40 C to +125 C TSSOP20 plastic thin shrink small outline package SOT360-1 20 leads body width 4.4 mm 74HCT7541PW-Q100Nexperia 74HC7541-Q100 74HCT7541-Q100 Octal Schmitt trigger buffer/line driver 3-state 4. Functional diagram A0 Y0 2 18 Y1 A1 3 17 Y2 A2 4 16 Y3 A3 5 15 1 & EN 19 Y4 A4 6 14 2 18 A5 Y5 3 17 7 13 4 16 A6 Y6 5 15 8 12 6 14 7 13 A7 Y7 9 11 8 12 9 11 OE1 1 19 OE2 aaa-000084 aaa-000085 Fig. 1. Logic symbol Fig. 2. IEC logic symbol 5. Pinning information 5.1. Pinning 74HC7541 74HC7541 74HCT7541 74HCT7541 OE1 1 20 V OE1 1 20 V CC CC A0 2 19 OE2 A0 2 19 OE2 A1 3 18 Y0 A1 3 18 Y0 A2 4 17 Y1 A2 4 17 Y1 A3 5 16 Y2 A3 5 16 Y2 A4 6 15 Y3 A4 6 15 Y3 A5 7 14 Y4 A5 7 14 Y4 A6 8 13 Y5 A6 8 13 Y5 A7 9 12 Y6 A7 9 12 Y6 GND 10 11 Y7 GND 10 11 Y7 aaa-000086 aaa-000087 Fig. 3. Pin configuration SOT163-1 (SO20) Fig. 4. Pin configuration SOT360-1 (TSSOP20) 74HC HCT7541 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 2 3 August 2021 2 / 14