74HC574D,652

74HC574 74HCT574 Octal D-type flip-flop positive edge-trigger 3-state Rev. 8 30 July 2021 Product data sheet 1. General description The 74HC574 74HCT574 is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Wide supply voltage range from 2.0 to 6.0 V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) Input levels: For 74HC574: CMOS level For 74HCT574: TTL level 3-state non-inverting outputs for bus oriented applications 8-bit positive, edge-triggered register Common 3-state output enable input ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 C to +85 C and from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC574D -40 C to +125 C SO20 plastic small outline package 20 leads SOT163-1 body width 7.5 mm 74HCT574D 74HC574PW -40 C to +125 C TSSOP20 plastic thin shrink small outline package SOT360-1 20 leads body width 4.4 mm 74HCT574PWNexperia 74HC574 74HCT574 Octal D-type flip-flop positive edge-trigger 3-state 4. Functional diagram 2 D0 Q0 19 3 D1 Q1 18 D2 4 Q2 17 5 D3 FF1 Q3 16 3-STATE to 6 D4 Q4 15 OUTPUTS FF8 7 D5 Q5 14 Q6 8 D6 13 9 D7 Q7 12 CP 11 1 OE mna800 Fig. 1. Functional diagram D0 D1 D2 D3 D4 D5 D6 D7 D Q D Q D Q D Q D Q D Q D Q D Q CP CP CP CP CP CP CP CP FF1 FF2 FF3 FF4 FF5 FF6 FF7 FF8 CP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 001aah077 Fig. 2. Logic diagram 11 C1 1 EN 11 2 19 1D CP 2 19 D0 Q0 3 18 3 18 D1 Q1 4 17 4 17 D2 Q2 5 16 5 16 D3 Q3 6 15 6 15 D4 Q4 7 14 7 14 D5 Q5 8 13 D6 Q6 8 13 9 12 D7 Q7 9 12 OE 1 mna798 mna446 Fig. 3. Logic symbol Fig. 4. IEC logic symbol 74HC HCT574 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 8 30 July 2021 2 / 15