INTEGRATED CIRCUITS
DATA SHEET
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The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT191
Presettable synchronous 4-bit
binary up/down counter
December 1990
Product specication
File under Integrated Circuits, IC06Philips Semiconductors Product specication
Presettable synchronous 4-bit binary
74HC/HCT191
up/down counter
FEATURES Overflow/underflow indications are provided by two types
of outputs, the terminal count (TC) and ripple clock (RC).
Synchronous reversible counting
The TC output is normally LOW and goes HIGH when a
Asynchronous parallel load
circuit reaches zero in the count-down mode or reaches
15 in the count-up-mode. The TC output will remain
Count enable control for synchronous expansion
HIGH until a state change occurs, either by counting or
Single up/down control input
presetting, or until U/D is changed. Do not use the TC
Output capability: standard
output as a clock signal because it is subject to decoding
spikes. The TC signal is used internally to enable the
I category: MSI
CC
RC output. When TC is HIGH and CE is LOW, the RC
output follows the clock pulse (CP). This feature simplifies
GENERAL DESCRIPTION
the design of multistage counters as shown in Figs 5
and 6.
The 74HC/HCT191 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
In Fig.5, each RC output is used as the clock input to the
(LSTTL). They are specified in compliance with JEDEC
next higher stage. It is only necessary to inhibit the first
standard no. 7A.
stage to prevent counting in all stages, since a HIGH on
CE inhibits the RC output pulse as indicated in the function
The 74HC/HCT191 are asynchronously presettable 4-bit
table. The timing skew between state changes in the first
binary up/down counters. They contain four master/slave
and last stages is represented by the cumulative delay of
flip-flops with internal gating and steering logic to provide
the clock as it ripples through the preceding stages. This
asynchronous preset and synchronous count-up and
can be a disadvantage of this configuration in some
count-down operation.
applications.
Asynchronous parallel load capability permits the counter
Fig.6 shows a method of causing state changes to occur
to be preset to any desired number. Information present on
simultaneously in all stages. The RC outputs propagate
the parallel data inputs (D to D ) is loaded into the counter
0 3
the carry/borrow signals in ripple fashion and all clock
and appears on the outputs when the parallel load (PL)
inputs are driven in parallel. In this configuration the
input is LOW. As indicated in the function table, this
duration of the clock LOW state must be long enough to
operation overrides the counting function.
allow the negative-going edge of the carry/borrow signal to
Counting is inhibited by a HIGH level on the count enable
ripple through to the last stage before the clock goes
(CE) input. When CE is LOW internal state changes are
HIGH. Since the RC output of any package goes HIGH
initiated synchronously by the LOW-to-HIGH transition of
shortly after its CP input goes HIGH there is no such
the clock input. The up/down (U/D) input signal determines
restriction on the HIGH-state duration of the clock.
the direction of counting as indicated in the function table.
In Fig.7, the configuration shown avoids ripple delays and
The CE input may go LOW when the clock is in either
their associated restrictions. Combining the TC signals
state, however, the LOW-to-HIGH CE transition must
from all the preceding stages forms the CE input for a
occur only when the clock is HIGH. Also, the U/D input
given stage. An enable must be included in each carry
should be changed only when either CE or CP is HIGH.
gate in order to inhibit counting. The TC output of a given
stage it not affected by its own CE signal therefore the
simple inhibit scheme of Figs 5 and 6 does not apply.
December 1990 2