74AVCH4T245BQ-Q10X

74AVCH4T245-Q100 4-bit dual supply translating transceiver with configurable voltage translation 3-state Rev. 3 12 March 2020 Product data sheet 1. General description The 74AVCH4T245-Q100 is a 4-bit, dual supply transceiver that enables bidirectional level translation. The device can be used as two 2-bit transceivers or as a 4-bit transceiver. It features two 2-bit input-output ports (nAn and nBn), a direction control input (nDIR), an output enable input (nOE) and dual supply pins (V and V ). Both V and V can be supplied with any CC(A) CC(B) CC(A) CC(B) voltage between 0.8 V and 3.6 V. This feature makes the device suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins nAn, nOE and nDIR are referenced to V and pins nBn are referenced to V . A HIGH on nDIR allows CC(A) CC(B) transmission from nAn to nBn and a LOW on nDIR allows transmission from nBn to nAn. The output enable input (nOE) can be used to disable the outputs so the buses are effectively isolated. The device is fully specified for partial power-down applications using I . The I circuitry OFF OFF disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either V or V are at GND level, both nAn and CC(A) CC(B) nBn outputs are in the high-impedance OFF-state. The bus hold circuitry on the powered-up side always stays active. The 74AVCH4T245-Q100 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range: V : 0.8 V to 3.6 V CC(A) V : 0.8 V to 3.6 V CC(B) Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: MIL-STD-883, method 3015 Class 3B exceeds 8000 V HBM JESD22-A114E Class 3B exceeds 8000 V MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 ) Maximum data rates: 380 Mbit/s ( 1.8 V to 3.3 V translation) 200 Mbit/s ( 1.1 V to 3.3 V translation) 200 Mbit/s ( 1.1 V to 2.5 V translation) 200 Mbit/s ( 1.1 V to 1.8 V translation) 150 Mbit/s ( 1.1 V to 1.5 V translation) 100 Mbit/s ( 1.1 V to 1.2 V translation)Nexperia 74AVCH4T245-Q100 4-bit dual supply translating transceiver with configurable voltage translation 3-state Suspend mode Bus hold on data inputs Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V I circuitry provides partial Power-down mode operation OFF Multiple package options DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AVCH4T245D-Q100 -40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74AVCH4T245PW-Q100 -40 C to +125 C TSSOP16 plastic thin shrink small outline package SOT403-1 16 leads body width 4.4 mm 74AVCH4T245BQ-Q100 -40 C to +125 C DHVQFN16 plastic dual in-line compatible SOT763-1 thermal enhanced very thin quad flat package no leads 16 terminals body 2.5 3.5 0.85 mm 4. Marking Table 2. Marking codes Type number Marking code 74AVCH4T245D-Q100 74AVCH4T245D 74AVCH4T245PW-Q100 CH4T245 74AVCH4T245BQ-Q100 H4T245 5. Functional diagram 13 12 11 10 1B1 1B2 2B1 2B2 V V CC(A) CC(B) 1OE 2OE 15 14 1DIR 2DIR 2 3 1A1 1A2 2A1 2A2 001aak280 4 5 6 7 Fig. 1. Logic symbol 74AVCH4T245 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 3 12 March 2020 2 / 25