74AUP2G241DC,125

74AUP2G241 Low-power dual buffer/line driver 3-state Rev. 9 1 December 2020 Product data sheet 1. General description The 74AUP2G241 provides a dual non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH level at pin 1OE causes output 1Y to assume a high-impedance OFF-state. A LOW level at pin 2OE causes output 2Y to assume a high-impedance OFF-state. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire V range from 0.8 V to 3.6 V. CC This device ensures a very low static and dynamic power consumption across the entire V range CC from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using I . The I circuitry OFF OFF disables the output, preventing the damaging backflow current through the device when it is powered down. This device has an input-disable feature, which allows floating input signals. The input 1A is disabled when the output enable input 1OE is HIGH. The input 2A is disabled when the output enable input 2OE is LOW. 2. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Low static power consumption I = 0.9 A (maximum) CC Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of V CC Input-disable feature allows floating input conditions I circuitry provides partial Power-down mode operation OFF Multiple package options Specified from -40 C to +85 C and -40 C to +125 CNexperia 74AUP2G241 Low-power dual buffer/line driver 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP2G241DC -40 C to +125 C VSSOP8 plastic very thin shrink small outline package 8 leads SOT765-1 body width 2.3 mm 74AUP2G241GT -40 C to +125 C XSON8 plastic extremely thin small outline package no leads SOT833-1 8 terminals body 1 1.95 0.5 mm 74AUP2G241GN -40 C to +125 C XSON8 extremely thin small outline package no leads SOT1116 8 terminals body 1.2 1.0 0.35 mm 74AUP2G241GS -40 C to +125 C XSON8 extremely thin small outline package no leads SOT1203 8 terminals body 1.35 1.0 0.35 mm 4. Marking Table 2. Marking codes Type number Marking code 1 74AUP2G241DC p41 74AUP2G241GT p41 74AUP2G241GN p1 74AUP2G241GS p1 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1OE 1Y 1A 1 EN1 2OE 2Y 2A 2 EN2 001aah730 001aah731 Fig. 1. Logic symbol Fig. 2. IEC logic symbol 74AUP2G241 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 9 1 December 2020 2 / 21