Product Information

74AUP2G126GD,125

74AUP2G126GD,125 electronic component of Nexperia

Datasheet
Buffers & Line Drivers 2CH NON-INVERT 3.6 V

Manufacturer: Nexperia
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 0.2574 ea
Line Total: USD 0.2574

0 - Global Stock
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
0 - Global Stock


Ships to you between Thu. 04 Apr to Wed. 10 Apr

MOQ : 1
Multiples : 1
1 : USD 0.2574
5 : USD 0.2516
50 : USD 0.2398
250 : USD 0.2071
1000 : USD 0.1872
2500 : USD 0.1814

0 - Global Stock


Ships to you between Thu. 04 Apr to Wed. 10 Apr

MOQ : 42
Multiples : 1
42 : USD 0.2492
100 : USD 0.225
250 : USD 0.2088
1000 : USD 0.2006

     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Number of Input Lines
Number of Output Lines
Polarity
Supply Voltage - Max
Supply Voltage - Min
High Level Output Current
Low Level Output Current
Minimum Operating Temperature
Maximum Operating Temperature
Mounting Style
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Output Type
Brand
Logic Family
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Propagation Delay Time
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74AUP2G126 Low-power dual buffer/line driver 3-state Rev. 9 11 February 2013 Product data sheet 1. General description The 74AUP2G126 provides the dual non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (nOE). A LOW level at pin nOE causes the output to assume a high-impedance OFF-state. This device has the input-disable feature, which allows floating input signals. The inputs are disabled when the output enable input nOE is LOW. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire V range from 0.8 V to 3.6 V. This device ensures a very low CC static and dynamic power consumption across the entire V range from 0.8 V to 3.6 V. CC This device is fully specified for partial power-down applications using I . The I OFF OFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. 2. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Low static power consumption I = 0.9 A (maximum) CC Latch-up performance exceeds 100 mA per JESD78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of V CC Input-disable feature allows floating input conditions I circuitry provides partial Power-down mode operation OFF Multiple package options Specified from 40 Cto+85 C and 40 Cto+125 C74AUP2G126 NXP Semiconductors Low-power dual buffer/line driver 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP2G126DC 40 C to +125 C VSSOP8 plastic very thin shrink small outline package 8 leads SOT765-1 body width 2.3 mm 74AUP2G126GT 40 C to +125 C XSON8 plastic extremely thin small outline package no leads SOT833-1 8 terminals body 1 1.95 0.5 mm 74AUP2G126GF 40 C to +125 C XSON8 extremely thin small outline package no leads SOT1089 8 terminals body 1.35 1 0.5 mm 74AUP2G126GD 40 Cto +125 C XSON8 plastic extremely thin small outline package no leads SOT996-2 8 terminals body 3 2 0.5 mm 74AUP2G126GM 40 C to +125 C XQFN8 plastic, extremely thin quad flat package no leads SOT902-2 8 terminals body 1.6 1.6 0.5 mm 74AUP2G126GN 40 C to +125 C XSON8 extremely thin small outline package no leads SOT1116 8 terminals body 1.2 1.0 0.35 mm 74AUP2G126GS 40 C to +125 C XSON8 extremely thin small outline package no leads SOT1203 8 terminals body 1.35 1.0 0.35 mm 4. Marking Table 2. Marking codes 1 Type number Marking code 74AUP2G126DC p26 74AUP2G126GT p26 74AUP2G126GF pN 74AUP2G126GD p26 74AUP2G126GM p26 74AUP2G126GN pN 74AUP2G126GS pN 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1Y 1A 1OE nY 2Y nA 2A 2OE nOE 001aah787 mna234 Fig 1. Logic symbol Fig 2. Logic diagram (one gate) 74AUP2G126 All information provided in this document is subject to legal disclaimers. NXP B.V. 2013. All rights reserved. Product data sheet Rev. 9 11 February 2013 2 of 24

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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