74AUP1G373GM,115

74AUP1G373 Low-power D-type transparent latch 3-state Rev. 8 19 May 2021 Product data sheet 1. General description The 74AUP1G373 is a single D-type transparent latch with 3-state output. While the latch-enable (LE) input is high, the Q output follows the data (D) input. When pin LE is LOW, the latch stores the information that was present at the D-input one set-up time preceding the HIGH-to-LOW transition of pin LE. When pin OE is LOW, the contents of the latch is available at the (Q) output. When pin OE is HIGH, the output goes to the high-impedance OFF-state. Operation of input pin OE does not affect the state of the latch. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures a very low static and dynamic power consumption across the entire V range CC from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using I . The I circuitry OFF OFF disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity Low static power consumption I = 0.9 A (maximum) CC Overvoltage tolerant inputs to 3.6 V Low noise overshoot and undershoot < 10 % of V CC I circuitry provides partial Power-down mode operation OFF Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Multiple package options Specified from -40 C to +85 C and -40 C to +125 CNexperia 74AUP1G373 Low-power D-type transparent latch 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1G373GW -40 C to +125 C SC-88 plastic surface-mounted package 6 leads SOT363 74AUP1G373GM -40 C to +125 C XSON6 plastic extremely thin small outline package no leads SOT886 6 terminals body 1 1.45 0.5 mm 74AUP1G373GN -40 C to +125 C XSON6 extremely thin small outline package no leads SOT1115 6 terminals body 0.9 1.0 0.35 mm 74AUP1G373GS -40 C to +125 C XSON6 extremely thin small outline package no leads SOT1202 6 terminals body 1.0 1.0 0.35 mm 4. Marking Table 2. Marking Type number Marking code 1 74AUP1G373GW aW 74AUP1G373GM aW 74AUP1G373GN aW 74AUP1G373GS aW 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram D D Q Q LE LE 3 D Q 4 1 C1 3 4 1 LE LE OE EN 6 6 OE 001aae247 001aae248 001aae249 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram 74AUP1G373 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 8 19 May 2021 2 / 21