74AUP1G11GF,132

74AUP1G11 Low-power 3-input AND gate Rev. 7 13 October 2021 Product data sheet 1. General description The 74AUP1G11 is a single 3-input AND gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire V range from 0.8 V to 3.6 V. This device is fully specified for CC partial power down applications using I . The I circuitry disables the output, preventing the OFF OFF potentially damaging backflow current through the device when it is powered down. 2. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V Low static power consumption I = 0.9 A (maximum) CC High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Overvoltage tolerant inputs to 3.6 V Low noise overshoot and undershoot < 10 % of V CC I circuitry provides partial Power-down mode operation OFF Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Multiple package options Specified from -40 C to +85 C and -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1G11GW -40 C to +125 C TSSOP6 plastic thin shrink small outline package 6 leads SOT363-2 body width 1.25 mm 74AUP1G11GM -40 C to +125 C XSON6 plastic extremely thin small outline package no leads SOT886 6 terminals body 1 1.45 0.5 mm 74AUP1G11GN -40 C to +125 C XSON6 extremely thin small outline package no leads SOT1115 6 terminals body 0.9 1.0 0.35 mm 74AUP1G11GS -40 C to +125 C XSON6 extremely thin small outline package no leads SOT1202 6 terminals body 1.0 1.0 0.35 mmNexperia 74AUP1G11 Low-power 3-input AND gate 4. Marking Table 2. Marking Type number Marking code 1 74AUP1G11GW pU 74AUP1G11GM pU 74AUP1G11GN pU 74AUP1G11GS pU 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram A & 1 A 1 3 4 B Y B Y 3 4 6 C 6 C 001aac033 001aac029 001aac030 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram 6. Pinning information 6.1. Pinning 74AUP1G11 74AUP1G11 A 1 6 C 74AUP1G11 A 1 6 C A 1 6 C GND 2 5 V CC GND 2 5 V CC GND 2 5 V CC B 3 4 Y B 3 4 Y B 3 4 Y 001aag918 001aag919 001aag917 Transparent top view Transparent top view Fig. 4. Pin configuration SOT363-2 Fig. 5. Pin configuration Fig. 6. Pin configuration SOT1115 (SC-88) SOT886 (XSON6) and SOT1202 (XSON6) 74AUP1G11 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2022. All rights reserved Product data sheet Rev. 7 13 October 2021 2 / 16