74ALVC244BQ

INTEGRATED CIRCUITS DATA SHEET 74ALVC244 Octal buffer/line driver 3-state Product specication 2003 Sep 08 Supersedes data of 2003 Aug 11Philips Semiconductors Product specication Octal buffer/line driver 3-state 74ALVC244 FEATURES DESCRIPTION Wide supply voltage range from 1.65 to 3.6 V The 74ALVC244 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most 3.6 V tolerant inputs/outputs advanced CMOS compatible TTL families. CMOS low power consumption The 74ALVC244 is an octal non-inverting buffer/line driver Direct interface with TTL levels (2.7 to 3.6 V) with 3-state outputs. The 3-state outputs are controlled by Power-down mode the output enable inputs 1OE and 2OE. A HIGH on nOE Latch-up performance exceeds 250 mA causes the outputs to assume a high-impedance OFF-state. Schmitt-trigger action at all inputs makes the Complies with JEDEC standard: circuit highly tolerant for slower input rise and fall times. JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8B/JESD36 (2.7 to 3.6 V) ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. QUICK REFERENCE DATA GND = 0 V T =25 C. amb SYMBOL PARAMETER CONDITIONS TYPICAL UNIT t /t propagation delay nAn to nYn V = 1.8 V C = 30 pF R =1k 2.7 ns PHL PLH CC L L V = 2.5 V C = 30 pF R = 500 2.0 ns CC L L V = 2.7 V C = 50 pF R = 500 2.3 ns CC L L V = 3.3 V C = 50 pF R = 500 2.2 ns CC L L C input capacitance 3.5 pF I C power dissipation capacitance per buffer V = 3.3 V notes 1 and 2 20 pF PD CC Notes 1. C is used to determine the dynamic power dissipation (P in W). PD D 2 2 P =C V f N+ (C V f ) where: D PD CC i L CC o f = input frequency in MHz i f = output frequency in MHz o C = output load capacitance in pF L V = supply voltage in Volts CC N = total load switching outputs 2 (C V f ) = sum of the outputs. L CC o 2. The condition is V = GND to V . I CC 2003 Sep 08 2