74AHC373PW,118

74AHC373 Octal D-type transparant latch 3-state Rev. 4 5 March 2019 Product data sheet 1. General description The 74AHC373 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC373 consists of eight D-type transparent latches featuring separate D-type inputs for each latch and 3-state true outputs for bus oriented applications. A latch enable input (LE) and an output enable input (OE) are common to all latches. When pin LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding Dn input changes. When pin LE is LOW, the latches store the information that is present at the Dn inputs, after a set-up time preceding the HIGH-to-LOW transition of LE. When pin OE is LOW, the contents of the 8 latches are available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. The 74AHC373 is functionally identical to the 74AHC573 74AHCT573, but has a different pin arrangement. 2. Features and benefits Balanced propagation delays All inputs have a Schmitt-trigger action Common 3-state output enable input Inputs accepts voltages higher than V CC Functionally identical to the 74AHC573 74AHCT573 Input levels at CMOS input level ESD protection: HBM EIA/JESD22-A114E exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101C exceeds 1000 V Specified from -40 C to +85 C and from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC373D -40 C to +125 C SO20 plastic small outline package 20 leads SOT163-1 body width 7.5 mm 74AHC373PW -40 C to +125 C TSSOP20 plastic thin shrink small outline package SOT360-1 20 leads body width 4.4 mmNexperia 74AHC373 Octal D-type transparant latch 3-state 4. Functional diagram D0 Q0 3 2 D1 Q1 4 5 D2 Q2 7 6 D3 Q3 8 9 LATCH 3-STATE D4 Q4 1 TO 8 OUTPUTS 13 12 Q5 D5 14 15 D6 Q6 17 16 D7 Q7 18 19 LE 11 OE 1 001aae050 Fig. 1. Functional diagram 1 OE EN 11 C1 LE 11 3 2 1D LE D0 Q0 3 2 D0 Q0 4 5 D1 Q1 4 5 D1 Q1 7 6 7 6 D2 Q2 D2 Q2 8 9 8 9 D3 Q3 D3 Q3 13 12 13 12 D4 Q4 D4 Q4 14 15 14 15 D5 Q5 D5 Q5 17 16 D6 Q6 17 16 D6 Q6 18 19 D7 Q7 18 19 OE D7 Q7 1 001aae048 001aae049 Fig. 2. Logic symbol Fig. 3. IEC logic symbol D0 D1 D2 D3 D4 D5 D6 D7 D Q D Q D Q D Q D Q D Q D Q D Q LATCH LATCH LATCH LATCH LATCH LATCH LATCH LATCH 1 2 3 4 5 6 7 8 LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 001aae052 Fig. 4. Logic diagram 74AHC373 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2019. All rights reserved Product data sheet Rev. 4 5 March 2019 2 / 13