Product Information

SY89875UMG

SY89875UMG electronic component of Microchip

Datasheet
Clock Drivers & Distribution 2.5V LVDS Output Clock Divider/Fanout (I Temp, Green)

Manufacturer: Microchip
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 10.2235 ea
Line Total: USD 10.2235

1 - Global Stock
Ships to you between
Thu. 11 Apr to Mon. 15 Apr
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
14 - Global Stock


Ships to you between
Fri. 12 Apr to Wed. 17 Apr

MOQ : 1
Multiples : 1

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SY89875UMG
Microchip

1 : USD 19.6818
10 : USD 18.507
30 : USD 18.0581
100 : USD 17.6673

1 - Global Stock


Ships to you between Thu. 11 Apr to Mon. 15 Apr

MOQ : 1
Multiples : 1

Stock Image

SY89875UMG
Microchip

1 : USD 10.2235
25 : USD 8.7745
100 : USD 8.073

     
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Precision Edge 2.5V, 2.0GHz ANY DIFF. IN-TO-LVDS Micrel, Inc. SY89875U Precision Edge PROGRAMMABLE CLOCK DIVIDER AND 1:2 SY89875U FANOUT BUFFER W/ INTERNAL TERMINATION FEATURES DESCRIPTION Integrated programmable clock divider and 1:2 This low-skew, low-jitter device is capable of accepting a fanout buffer high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal and dividing down the frequency Guaranteed AC performance over temperature and using a programmable divider to create a lower speed voltage: version of the input clock. Available divider ratios are 2, 4, 8 > 2.0GHz f MAX and 16, or straight pass-through. < 200ps t /t r f < 15ps within device skew The differential input buffer has a unique internal termination design that allows access to the termination Low jitter design: network through a V pin. This feature allows the device to < 10ps total jitter T PP easily interface to different logic standards. A V < 1ps cycle-to-cycle jitter REF-AC RMS reference is included for AC-coupled applications. Unique input termination and V Pin for DC-coupled T The /RESET input asynchronously resets the divider. In and AC-coupled Inputs CML, PECL, LVDS and the pass-through function (divide by 1) the /RESET HSTL synchronously enables or disables the outputs on the next LVDS compatible outputs falling edge of IN (rising edge of /IN). TTL/CMOS inputs for select and reset Parallel programming capability Programmable divider ratios of 1, 2, 4, 8 and 16 Low voltage operation 2.5V Output disable function 40C to 85C temperature range Available in 16-pin (3mm x 3mm) MLF package TYPICAL PERFORMANCE APPLICATIONS OC-12 to OC-3 Translator/Divider SONET/SDH line cards Transponders High-end, multiprocessor servers CML/LVPECL/LVDS LVDS Divide-by-4 622MHz 155.5MHz Clock In Clock Out FUNCTIONAL BLOCK DIAGRAM 622MHz In IN /IN 155.5MHz Out Q0 % /Q0 United States Patent No. RE44,134 Precision Edge is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc. Rev.: D Amendment: /0 M9999-082407 1 Issue Date: August 2007 hbwhelp micrel.com or (408) 955-1690 Precision Edge Micrel, Inc. SY89875U PACKAGE/ORDERING INFORMATION Ordering Information(1) Package Operating Package Lead 16 15 14 13 Part Number Type Range Marking Finish Q0 1 12 IN SY89875UMI MLF-16 Industrial 875U Sn-Pb /Q0 2 11 VT (2) SY89875UMITR MLF-16 Industrial 875U Sn-Pb Q1 3 10 VREF-AC (3) SY89875UMG MLF-16 Industrial 875U with NiPdAu /Q1 4 9 /IN Pb-Free bar line indicator Pb-Free 5 6 7 8 (2, 3) SY89875UMGTR MLF-16 Industrial 875U with NiPdAu Pb-Free bar line indicator Pb-Free Notes: 1. Contact factory for die availability. Dice are guaranteed at T = 25C, DC Electricals only. A 2. Tape and Reel. 16-Pin MLF (MLF-16) 3. Pb-Free package is recommended for new designs. PIN DESCRIPTION Pin Number Pin Name Pin Function 12, 9 IN, /IN Differential Input: Internal 50 termination resistors to V input. Flexible input accepts any T differential input. See Input Interface Applications section. 1, 2, 3, 4 Q0, /Q0 Differential Buffered LVDS Outputs: Divided by 1, 2, 4, 8 or 16. See Truth Table. Q1, /Q1 Unused output pairs must be terminated with 100 across the different pair. 16, 15, 5 S0, S1, S2 Select Pins: See Truth Table. LVTTL/CMOS logic levels. Internal 25k pull-up resistor. Logic HIGH if left unconnected (divided by 16 mode.) Input threshold is V /2. CC 6 NC No Connect. 8 /RESET, LVTTL/CMOS Logic Levels: Internal 25k pull-up resistor. Logic HIGH if left unconnected. /DISABLE Apply LOW to reset the divider (divided by 2, 4, 8 or 16 mode). Also acts as a disable/enable function. The reset and disable function occurs on the next high-to-low clock input transition. Input threshold is V /2. CC 10 VREF-AC Reference Voltage: Equal to V 1.4V (approx.). Used for AC-coupled applications only. CC Decouple the V pin with a 0.01F capacitor. See Input Interface Applications section. REFAC 11 VT Termination Center-Tap: For CML or LVDS inputs, leave this pin floating. Otherwise, See Figures 4a to 4f, Input Interface Applications section. 7, 14 VCC Positive Power Supply: Bypass with 0.1F//0.01F low ESR capacitor. 13 GND Ground. Exposed pad must be connected to the same potential as the GND pin. Exposed TRUTH TABLE (1) /RESET S2 S1 S0 Outputs 1 0 X X Reference Clock (pass through) 1 1 0 0 Reference Clock 2 1 1 0 1 Reference Clock 4 1 1 1 0 Reference Clock 8 1 1 1 1 Reference Clock 16 (1) 0 X X X Q = LOW, /Q = HIGH Clock Disable Note 1. Reset/Disable function is asserted on the next clock input (IN, /IN) high-to-low transition. M9999-082407 2 hbwhelp micrel.com or (408) 955-1690 S2 S0 NC S1 VCC VCC /RESET GND

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Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
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