SY89312V 3.3V/5V, 4GHz PECL/ECL 2 Clock Generator Precision Edge General Description The SY89312V is an integrated 2 divider with differential Precision Edge clock inputs. It is functionally equivalent to the SY100EP32V but in an ultra-small 8-pin QFN package Features that features a 70% smaller footprint. Guaranteed AC performance over temperature and The V pin, an internally generated voltage supply, is voltage: BB >4GHz f input available for this device only. For single-ended input MAX conditions, the unused differential input is connected to V BB <160ps t /t r f as a switching reference voltage. V can also bias AC- BB <440ps t pd coupled inputs. When used, decouple V and V via a BB CC 3.3V and 5V power supply operation 0.01F capacitor and limit current sourcing or sinking to 100k ECL/PECL-compatible I/O 0.5mA. When not in use, V should be left open. BB Internal 75K input pull-down resistors The reset pin is asynchronous and is asserted when it is Wide operating temperature range: 40C to +85C high. Upon power-up, the internal flip-flops will be in a Available in ultra-small 8-pin 2mm 2mm QFN package random state the reset allows for the synchronous use of multiple SY89312Vs in a system. (1) Datasheets and support documentation are available on Truth Table Micrels web site at: www.micrel.com. CLK /CLK RESET Q /Q X X H L H L F F Note: 1. F = Divide by 2 function. Precision Edge is a registered trademark of Micrel, Inc. Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 Micrel, Inc. SY89312V Ordering Information Part Number Package Type Operating Range Package Marking Lead Finish (2) SY89312VMGTR 8-pin 2mm 2mm QFN Industrial 312 with Pb-Free Bar Line Indicator Pb-Free NiPdAu Note: 2. Pb-Free package is recommended for new designs. Pin Configuration 8-Pin 2mm 2mm QFN Pin Description Pin Number Pin Name Type Pin Function 100K Differential PECL/ECL Input: Internal 75k pull-down resistor. If left open, pin 2, 3 CLK, /CLK ECL/PECL defaults LOW (see Input Interface Applications section for single-ended inputs). Input 100K Differential PECL/ECL Output: Output CLK input divided by 2 (see Output 7, 6 Q, /Q ECL/PECL Interface Applications section for recommendations on terminations). Output Positive Power 8 VCC Positive Power Supply: Bypass with 0.1 citoFr/s./0. 01F low ES Supply Negative Negative Power Supply: VEE and exposed pad (ePad) must be tied to most 5 VEE, ePad Power Supply negative supply. For PECL/LVPECL connect to ground. Reference Bias Reference Voltage: VCC1.4V. Used as reference voltage for single- ended 4 VBB Voltage inputs or AC-coupling to the CLK, /CLK inputs. Maximum sink/source is 0.5mA Output (see Input Interface Applications section). 100k 1 Reset ECL/PECL Single-Ended Input: PECL/ECL asynchronous reset. Input Revision 2.0 June 25, 2013 2 hbwhelp micrel.com or (408) 955-1690