SY100EP195VTG-TR

SY100EP195V 3.3V/5V 1.6 GHz Programmable Delay Features General Description Pin-for-Pin, Plug-In Compatible to the ON The SY100EP195V is a programmable delay line, Semiconductor MC100EP195 varying the time a logic signal takes to traverse from IN to Q. This delay can vary from about 2.1 ns to about Maximum Frequency >1.6 GHz 10.8 ns. The input can be PECL, LVPECL, NECL, or Programmable Range: 2.1 ns to 10.8 ns LVNECL. 1 0 ps Increments The delay varies in discrete steps based on a control PECL Mode Operating Range: V = 3.0V to CC word presented to the SY100EP195V. The 10-bit width 5.5V with V = 0V EE of this latched control register allows for delay NECL Mode Operating Range: V = 0V with CC increments of approximately 10 ps. V = 3.0V to 5.5V EE An eleventh control bit allows the cascading of multiple Open Input Default State SY100EP195V devices, for a wider delay range. Each Safety Clamp on Inputs additional SY100EP195V effectively doubles the delay A Logic-High on the /EN pin will Force Q to range available. Logic-Low For maximum flexibility, the control register interface D 0:10 Can Accept Either ECL, CMOS, or TTL accepts CMOS or TTL level signals, as well as the input Inputs level at the IN, /IN pins. V Output Reference Voltage BB Available in a 32-Pin TQFP Package Package Type Applications SY100EP195V Clock De-skewing 32-Lead TQFP (T) Timing Adjustment (Top View) Aperture Centering 32 31 30 29 28 27 26 25 D8 1 24 VEE 2 23 D9 D0 3 22 D10 VCC 4 21 IN Q 5 20 /IN /Q 6 19 VCC VBB VCC VEF 7 18 8 17 NC VCF 9 10111213141516 2019 Microchip Technology Inc. DS20006194A-page 1 D7 VEE D6 LEN SETMIN D5 SETMAX D4 VEE VCC D3 /CASCADE D2 CASCADE D1 /ENSY100EP195V Typical Application Circuit Data Signal D Q+ of Unknown Phase Flip-Flop SY100EP195V CLOCK+ IN Q CK Q /IN /Q CLOCK D 9:0 CONTROL LOGIC Functional Block Diagram 2DS20006194A-page 2019 Microchip Technology Inc.