Product Information

SY100EP111UTG

SY100EP111UTG electronic component of Microchip

Datasheet
Buffers & Line Drivers 2.5-5V 1:10 PECL Fanout Buffer (I Temp, Green)

Manufacturer: Microchip
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

221: USD 5.2907 ea
Line Total: USD 1169.2447

214 - Global Stock
Ships to you between
Thu. 04 Apr to Wed. 10 Apr
MOQ: 221  Multiples: 221
Pack Size: 221
Availability Price Quantity
21 - Global Stock


Ships to you between Thu. 04 Apr to Wed. 10 Apr

MOQ : 1
Multiples : 1

Stock Image

SY100EP111UTG
Microchip

1 : USD 6.7436
25 : USD 6.7436
100 : USD 6.7436

17 - Global Stock


Ships to you between Wed. 10 Apr to Fri. 12 Apr

MOQ : 1
Multiples : 1

Stock Image

SY100EP111UTG
Microchip

1 : USD 7.3485
25 : USD 6.3135
100 : USD 5.7385

214 - Global Stock


Ships to you between Thu. 04 Apr to Wed. 10 Apr

MOQ : 221
Multiples : 221

Stock Image

SY100EP111UTG
Microchip

221 : USD 5.2907

21 - Global Stock


Ships to you between Thu. 04 Apr to Wed. 10 Apr

MOQ : 2
Multiples : 1

Stock Image

SY100EP111UTG
Microchip

2 : USD 6.7436

     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Number of Input Lines
Number of Output Lines
Polarity
Supply Voltage - Max
Supply Voltage - Min
Operating Supply Current
Minimum Operating Temperature
Maximum Operating Temperature
Mounting Style
Package / Case
Packaging
Output Type
Series
Supply Current
Brand
Propagation Delay Time
Factory Pack Quantity :
Cnhts
Hts Code
Mxhts
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Precision Edge Micrel, Inc. SY100EP111U 2.5V/3.3V 1:10 DIFFERENTIAL Precision Edge SY100EP111U LVPECL/LVECL/HSTL CLOCK DRIVER FEATURES 2.5V and 3.3V power supply options Guaranteed AC parameters over temperature: Precision Edge f = 3GHz MAX < 25ps output-to-output skew DESCRIPTION < 250ps t /t r f < 400ps propagation delay The SY100EP111U is a high-speed, low skew 1-to-10 differential fanout buffer designed for clock distribution in Wide temperature range: 40C to +85C new, high-performance systems. The internal 2:1 mux Differential design allows the input to select between two differential clock V output for single-ended input applications BB sources. Fully compatible with industry standard 100K I/O The device is specifically designed for low skew. The levels interconnect scheme and metal layout are carefully optimized for minimal gate-to-gate skew within the device. Available in 32-pin TQFP package Wafer characterization and process control ensure consistent distribution of propagation delay from lot to lot. The V output is intended for use as a reference BB voltage for single-ended reception of ECL signals to that device only. When using V for this purpose, it is BLOCK DIAGRAM BB recommended that V is decoupled to V via a 0.01F BB CC capacitor. Q 0 /Q 0 Q 1 /Q 1 Q 2 /Q 2 Q 3 /Q 3 CLK0 V 75k EE Q 0 4 /CLK0 /Q 4 75k 75k Q 5 V V EE CC /Q 5 CLK1 V 75k EE 1 Q 6 /CLK1 /Q 6 75k 75k Q V V 7 EE CC /Q 7 CLK SEL 75k Q 8 V /Q EE 8 V Q BB 9 /Q 9 Precision Edge is a registered trademark of Micrel, Inc. Rev.: F Amendment: /0 M9999-021511 1 hbwhelp micrel.com or (408) 955-1690 Issue Date: December 2005 Precision Edge Micrel, Inc. SY100EP111U PACKAGE/ORDERING INFORMATION (1) Ordering Information Package Operating Package Lead 32 31 30 29 28 27 26 25 Part Number Type Range Marking Finish VCC 1 24 Q3 CLK SEL 2 23 /Q3 SY100EP111UTI T32-1 Industrial 100EP111UTI Sn-Pb CLK0 3 22 Q4 (2) SY100EP111UTITR T32-1 Industrial 100EP111UTI Sn-Pb Top View /CLK0 4 21 /Q4 TQFP (3) SY100EP111UTG T32-1 Industrial 100EP111UTG with Pb-Free 5 20 Q5 VBB T32-1 Pb-Free bar-line indicator NiPdAu 6 19 /Q5 CLK1 (2, 3) /CLK1 7 18 Q6 SY100EP111UTGTR T32-1 Industrial 100EP111UTG with Pb-Free VEE 8 17 /Q6 Pb-Free bar-line indicator NiPdAu 910 111213 1415 16 (2, 4) SY100EP111UTGTX T32-1 Industrial 100EP111UTG with Pb-Free Pb-Free bar-line indicator NiPdAu Notes: 1. Contact factory for die availability. Dice are guaranteed at T = 25C, DC Electricals only. A 32-Pin TQFP (T32-1) 2. Tape and Reel. 3. Pb-Free package is recommended for new designs. 4. EIA specification orientation. PIN NAMES FUNCTION TABLE Pin Function CLK SEL Active Input CLK0, /CLK0 LVPECL, LVECL, HSTL Clock Inputs: 0 CLK0, /CLK0 CLK0 input includes a 75k pull-down. Default 1 CLK1, /CLK1 is low if left floating. /CLK0 includes an internal 75k pull-up and pull-down. Default state is V /2. CC CLK1, /CLK1 LVPECL, LVECL, HSTL Clock Inputs: CLK input includes a 75k pull-down. Default is low if left floating. /CLK includes an internal 75k pull-up and pull-down. Default state is V /2. CC Q0 to Q9 LVPECL/LVECL Outputs. /Q0 to /Q9 Complementary LVPECL/LVECL Outputs. CLK SEL LVPECL/LVECL Clock Select Input: Internal 75k resistor connected to V . When left EE floating, the default condition is LOW. V Reference Voltage: AC coupled or single- BB ended input applications. V Positive Power Supply: Bypass with 0.1F// CC 0.01F low ESR capacitors. V Negative Power Supply: LVPECL operation, EE connect to GND. M9999-021511 2 hbwhelp micrel.com or (408) 955-1690 VCC VCC Q0 /Q9 /Q0 Q9 Q1 /Q8 /Q1 Q8 Q2 /Q7 Q7 /Q2 VCC VCC

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8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
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