MCP47FEB11A0-E/ST

MCP47FEBXX 8-/10-/12-Bit Single/Dual Voltage Output Nonvolatile Digital-to-Analog Converters with IC Interface Features Package Types MCP47FEBX1 Operating Voltage Range: TSSOP - 2.7V to 5.5V - Full Specifications Single - 1.8V to 2.7V - Reduced Device Specifications Output Voltage Resolutions: V 1 8 SDA DD - 8-bit: MCP47FEB0X (256 Steps) V 2 7 SCL REF0 - 10-bit: MCP47FEB1X (1024 Steps) V LAT0/HVC 3 6 OUT0 - 12-bit: MCP47FEB2X (4096 Steps) NC 4 5 V SS Rail-to-Rail Output Fast Settling Time of 6 s (typical) MCP47FEBX2 TSSOP DAC Voltage Reference Source Options: Dual - Device V DD -External V pin (buffered or unbuffered) REF V 1 8 SDA DD - Internal Band Gap (1.22V typical) (1) V 2 7 SCL REF Output Gain Options: (1) V LAT /HVC 3 6 OUT0 - Unity (1x) V 4 5 V OUT1 SS - 2x (when not using internal V as voltage DD source) Note 1: This pins signal can be connected to DAC0 and/or DAC1. Nonvolatile Memory (EEPROM): - User-programmed Power-on Reset (POR)/Brown-out Reset (BOR) output setting General Description recall and device configuration bits The MCP47FEBXX are Single- and Dual-channel 8-bit, - Auto Recall of Saved DAC register setting 10-bit, and 12-bit buffered voltage output Digital-to- - Auto Recall of Saved Device Configuration Analog Converters (DAC) with nonvolatile memory and (Voltage Reference, Gain, Power-Down) 2 an I C serial interface. Power-on/Brown-out Reset Protection The V pin, the device V or the internal band gap REF DD Nonvolatile Memory Write Protect (WP) Bit voltage can be selected as the DACs reference Power-Down Modes: voltage. When V is selected, V is connected DD DD - Disconnects output buffer (High Impedance) internally to the DAC reference circuit. When the V REF - Selection of V pull-down resistors pin is used, the user can select the output buffers gain OUT (100 k or 1 k ) to be 1 or 2. When the gain is 2, the V pin voltage REF should be limited to a maximum of V /2. Low Power Consumption: DD 2 - Normal operation: <180 A (Single), 380 A These devices have a two-wire I C-compatible serial (Dual) interface for Standard (100kHz), Fast (400 kHz) or High-Speed (1.7 MHz and 3.4 MHz) modes. - Power-down operation: 650 nA typical - EEPROM write cycle (1.9 mA maximum) 2 Applications I C Interface: - Slave address options: four predefined Set Point or Offset Trimming addresses or user programmable (all 7 bits) Sensor Calibration - Standard (100 kbps), Fast (400 kbps), and Low-Power Portable Instrumentation High-Speed (up to 3.4 Mbps) modes PC Peripherals Package Types: 8-lead TSSOP Data Acquisition Systems Extended Temperature Range: -40C to +125C Motor Control 2015 Microchip Technology Inc. DS20005375A-page 1MCP47FEBXX MCP47FEBX1 Device Block Diagram (Single-Channel Output) Power-up/ V DD Brown-out V Memory (32x16) SS Control DAC0 (Vol and NV) 2 I C Serial SDA VREF (Vol and NV) Interface Power-down (Vol and NV) SCL Module and Gain (Vol and NV) Control Logic Status (Vol) (WiperLock Slave Address (NV) Technology) VREF1:VREF0 V DD and PD1:PD0 Gain PD1:PD0 and V VREF1:VREF0 Band Gap BG Op (1.22V) Amp V OUT0 PD1:PD0 V + REF0 (1) - V PD1:PD0 SS V DD VREF1:VREF0 LAT0/HVC Note 1: If Internal Band Gap is selected, this buffer has a 2x gain. If the G bit = 1, this is a total gain of 4. DS20005375A-page 2 2015 Microchip Technology Inc. Resistor Ladder 1k 100 k