MCP3912 3V Four-Channel Analog Front End Features: Description: Four Synchronous Sampling 24-Bit Resolution The MCP3912 is a 3V four-channel Analog Front End Delta-Sigma A/D Converters (AFE) containing four synchronous sampling Delta- Sigma Analog-to-Digital Converters (ADC), four PGAs, 93.5 dB SINAD, -107 dBc Total Harmonic th phase delay compensation block, low-drift internal volt- Distortion (THD) (up to 35 Harmonic), 112 dBFS age reference, Digital Offset and Gain Error Calibration SFDR for Each Channel registers, and high-speed 20 MHz SPI-compatible Enables 0.1% Typical Active Power Measurement serial interface. Error Over a 10,000:1 Dynamic Range The MCP3912 ADCs are fully configurable, with Advanced Security Features: features, such as 16/24-bit resolution, Oversampling - 16-Bit Cyclic Redundancy Check (CRC) Ratio (OSR) from 32 to 4096, gain from 1x to 32x, Checksum on All Communications for Secure independent shutdown and Reset, dithering and auto- Data Transfers zeroing. The communication is largely simplified with - 16-Bit CRC Checksum and Interrupt Alert for 8-bit commands, including various continuous Read/ Register Map Configuration Write modes and 16/24/32-bit data formats that can be - Register Map Lock with 8-Bit Secure Key accessed by the Direct Memory Access (DMA) of an , DV 2.7V-3.6V AV 8, 16 or 32-bit MCU. A separate Data Ready pin is also DD DD included that can directly be connected to an Interrupt Programmable Data Rate Up to 125 ksps: Request (IRQ) input of an MCU. - 4 MHz Maximum Sampling Frequency - 16 MHz Maximum Master Clock The MCP3912 includes advanced security features to secure the communications and the configuration set- Oversampling Ratio Up to 4096 tings, such as a CRC-16 checksum on both serial data Ultra-Low Power Shutdown Mode with < 10 A outputs and static register map configuration. It also -122 dB Crosstalk Between Channels includes a register map lock through an 8-bit secure key Low Drift 1.2V Internal Voltage Reference: to stop unwanted WRITE commands from processing. 9 ppm/C The MCP3912 is capable of interfacing with a variety of Differential Voltage Reference Input Pins voltage and current sensors, including shunts, current High-Gain PGA on Each Channel (up to 32 V/V) transformers, Rogowski coils and Hall effect sensors. Phase Delay Compensation with 1 s Time Resolution Applications: Separate Data Ready Pin for Easy Polyphase Energy Meters Synchronization Energy Metering and Power Measurement Individual 24-Bit Digital Offset and Gain Error Automotive Correction for Each Channel Portable Instrumentation High-Speed 20 MHz SPI Interface with Mode 0,0 and 1,1 Compatibility Medical and Power Monitoring Continuous Read/Write Modes for Minimum Audio/Voice Recognition Communication Time with Dedicated 16/32-Bit Modes Available in 28-Lead QFN and 28-Lead SSOP Packages Extended Temperature Range: -40C to +125C 2014-2019 Microchip Technology Inc. DS20005348B-page 1MCP3912 Package Type MCP3912 MCP3912 SSOP 5x5 QFN* AV DV 1 28 DD DD CH0+ 2 27 RESET CH0- SDI 28 27 26 25 24 23 22 3 26 CH1- SDO 4 25 CH1- 1 21 SDI CH1+ 5 24 SCK 2 20 SDO CH1+ CH2+ 6 23 CS CH2+ 3 19 SCK EP CH2- 7 22 OSC2 18 CS CH2- 4 29 CH3- 8 21 OSC1/CLKI 17 OSC2 CH3- 5 CH3+ 9 20 D GND 16 OSC1/CLKI CH3+ 6 NC NC 10 19 D 15 NC 7 GND NC 11 18 DR 89 10 11 12 13 14 D NC 12 17 GND NC 13 16 A GND REFIN+/OUT 14 15 REFIN- * Includes Exposed Thermal Pad (EP) see Table 1-3. Functional Block Diagram AVDD DVDD REFIN+/OUT Voltage VREFEXT AMCLK Xtal Oscillator Reference OSC1 MCLK Clock + Vref Generation DMCLK/DRCLK OSC2 - REFIN- Vref- Vref+ DMCLK OSR<2:0> OFFCAL CH0 GAINCAL CH0 OSR/2- PRE<1:0> <23:0> <23:0> PHASE1 <11:0> CH0+ + + X MOD<3:0> DATA CH0<23:0> CH0- - 3 PGA Phase SINC + Offset Gain 1 Modulator Shifter SINC Cal. Cal. OFFCAL CH1 GAINCAL CH1 <23:0> <23:0> OSR/2 CH1+ + + X MOD<7:4> DATA CH1<23:0> CH1- - 3 PGA Phase SINC + Offset Gain 1 Modulator Shifter SINC Cal. Cal. OSR/2- OFFCAL CH2 GAINCAL CH2 PHASE1 <23:12> <23:0> <23:0> CH2+ + X Digital SPI MOD<11:8> DATA CH2<23:0> CH2- - Interface 3 Phase SINC + Offset Gain PGA 1 Modulator Shifter SINC Cal. Cal. OFFCAL CH3 GAINCAL CH3 <23:0> <23:0> OSR/2 CH3+ + DR X SDO MOD<15:12> DATA CH3<23:0> CH3- - 3 PGA Phase SINC + Offset Gain 1 Modulator Shifter SINC Cal. Cal. RESET SDI SCK CS POR POR AV DV DD DD Monitoring Monitoring ANALOG DIGITAL AGND D GND DS20005348B-page 2 2014-2019 Microchip Technology Inc. REFIN+/ CH0- OUT CH0+ REFIN- A A GND GND AV AV DD DD DV DD DV DD D GND D GND RESET DR