ATWILC1000B-UU-T

ATWILC1000B-MUT ATWILC1000B-MUT IEEE 802.11 b/g/n Link Controller SoC Introduction The ATWILC1000B is a single chip IEEE 802.11 b/g/n Radio/Baseband/MAC link controller optimized for low-power mobile applications. The ATWILC1000B supports single stream 1x1 802.11n mode providing up to 72 Mbps PHY rate. The ATWILC1000B features a fully integrated Power Amplifier (PA), Low Noise Amplifier (LNA), Switch, and Power Management. The ATWILC1000B offers very low-power consumption while simultaneously providing high performance and minimal bill of materials. The ATWILC1000B provides multiple peripheral interfaces including Universal Asynchronous Receiver/ 2 Transmitter (UART), Serial Peripheral Interface (SPI), Inter-Integrated Circuit (I C), and Secure Digital Input Output (SDIO). The clock source for the ATWILC1000B is provided by an external crystal at 26 MHz. The ATWILC1000B is available in both QFN and Wafer Level Chip Scale Package (WLCSP) packaging. Features IEEE 802.1 b/g/n 20 MHz (1x1) Solution Single Spatial Stream in 2.4 GHz ISM Band Integrated PA and T/R Switch Superior Sensitivity and Range via Advanced PHY Signal Processing Advanced Equalization and Channel Estimation Advanced Carrier and Timing Synchronization Wi-Fi Direct and Soft-AP Support Supports IEEE 802.11 WEP, WPA, WPA2 Security Superior MAC Throughput via Hardware Accelerated Two-Level A-MSDU/A-MPDU Frame Aggregation and Block Acknowledgment On-Chip Memory Management Engine to Reduce Host Load 2 SPI, SDIO, and I C Host Interfaces Operating Temperature Ranges from -40C to +85C Power Save Modes: <1 A Deep Power-Down mode typical at 3.3V I/O 280 A Doze mode with chip settings preserved (used for beacon monitoring) On-chip low-power sleep oscillator Fast host wake up from Doze mode by a pin or host I/O transaction Datasheet DS70005386A-page 1 2018 Microchip Technology Inc. ATWILC1000B-MUT Table of Contents Introduction......................................................................................................................1 Features.......................................................................................................................... 1 1. Ordering Information and IC Marking........................................................................ 4 2. Block Diagram........................................................................................................... 5 3. Pinout and Package Information............................................................................... 6 3.1. Pin Description............................................................................................................................. 6 3.2. Package Description.................................................................................................................. 13 4. Electrical Specifications...........................................................................................15 4.1. Absolute Ratings........................................................................................................................ 15 4.2. Recommended Operating Conditions........................................................................................ 15 4.3. DC Electrical Characteristics......................................................................................................16 5. Clocking...................................................................................................................17 5.1. Crystal Oscillator........................................................................................................................ 17 5.2. Low-Power Oscillator................................................................................................................. 18 6. CPU and Memory Subsystem................................................................................. 19 6.1. Processor................................................................................................................................... 19 6.2. Memory Subsystem....................................................................................................................19 6.3. Nonvolatile Memory (eFuse)...................................................................................................... 19 7. WLAN Subsystem................................................................................................... 21 7.1. MAC........................................................................................................................................... 21 7.2. PHY............................................................................................................................................22 7.3. Radio..........................................................................................................................................22 8. External Interfaces...................................................................................................27 2 8.1. I C Slave Interface..................................................................................................................... 27 2 8.2. I C Master Interface................................................................................................................... 28 8.3. SPI Slave Interface.....................................................................................................................29 8.4. SPI Master Interface...................................................................................................................31 8.5. SDIO Slave Interface..................................................................................................................33 8.6. UART Debug Interface...............................................................................................................34 8.7. GPIOs.........................................................................................................................................35 9. Power Management................................................................................................ 36 9.1. Power Architecture.....................................................................................................................36 9.2. Power Consumption...................................................................................................................37 9.3. Power-Up/Down Sequence........................................................................................................39 9.4. Digital I/O Pin Behavior During Power-up Sequences............................................................... 40 DS70005386A-page 2 Datasheet 2018 Microchip Technology Inc.