Platform Manager In-System Programmable Power and Digital Board Management February 2012 Data Sheet DS1036 Features Block Diagram Precision Voltage Monitoring Increases 10-Bit 12 Analog Margin/Trim Reliability ADC Voltage 12 independent analog monitor inputs Monitor MOSFET Differential inputs for remote ground sense Inputs Drivers Two programmable threshold comparators per 48-Macrocell CPLD analog input Digital Open Drain Hardware window comparison Inputs Outputs 2 10-bit ADC for I C monitoring Power FPGA 4 Timers High-Voltage FET Drivers Enable JTAG I/O JTAG I/O Integration Power supply ramp up/down control Configuration Memory Programmable current and voltage output 640-LUT Digital I/O Independently configurable for FET control or FPGA Power digital output 2 II C/SMBus Power Supply Margin and Trim Functions Trim and margin up to eight power supplies 2 Description Dynamic voltage control through I C Independent Digital Closed-Loop Trim function The Lattice Platform Manager integrates board power for each output management (hot-swap, sequencing, monitoring, reset Programmable Timers Increase Control generation, trimming and margining) and digital board Flexibility management functions (reset tree, non-volatile error Four independent timers logging, glue logic, board digital signal monitoring and 32 s to 2 second intervals for timing sequences control, system bus interface, etc.) into a single inte- PLD Resources Integrate Power and Digital grated solution. Functions 48-macrocell CPLD The Platform Manager device provides 12 independent 640 LUT4s FPGA analog input channels to monitor up to 12 power supply Up to 107 digital I/Os test points. Up to 12 of these input channels can be Up to 6.1 Kbits distributed RAM monitored through differential inputs to support remote Programmable sysIO Buffer Supports a ground sensing. Each of the analog input channels is Range of Interfaces monitored through two independently programmable LVCMOS 3.3/2.5/1.8/1.5/1.2 comparators to support both high/low and in-bounds/ LVTTL out-of-bounds (window-compare) monitor functions. Up System-Level Support to six general purpose 5V tolerant digital inputs are also Single 3.3V supply operation provided for miscellaneous control functions. Industrial temperature range: -40C to +85C There are 16 open-drain digital outputs that can be In-System Programmability Reduces Risk used for controlling DC-DC converters, low-drop-out Integrated non-volatile configuration memory regulators (LDOs) and opto-couplers, as well as for JTAG programming interface supervisory and general purpose logic interface func- Package Options tions. Four of these outputs (HVOUT1-HVOUT4) may 128-pin TQFP be configured as high-voltage MOSFET drivers. In high- 208-ball ftBGA voltage mode these outputs can provide up to 12V for RoHS compliant and halogen-free driving the gates of n-channel MOSFETs so that they can be used as high-side power switches controlling the supplies with a programmable ramp rate for both ramp up and ramp down. 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 DS1036 01.3Platform Manager Data Sheet The board power management function can be implemented using an internal 48-macrocell CPLD. The status of all of the comparators on the analog input channels as well as the general purpose digital inputs are used as inputs by the CPLD array, and all digital outputs (open-drain as well as HVOUT) may be controlled by the CPLD. Four independently programmable timers can create delays and time-outs ranging from 32 s to 2 seconds. The Platform Manager device incorporates up to eight DACs for generating trimming voltage to control the output voltage of a DC-DC converter. Additionally, each power supply output voltage can be maintained typically within 0.5% tolerance across various load conditions using the Digital Closed Loop Control mode. 2 The internal 10-bit A/D converter can both be used to monitor the VMON voltage through the I C bus as well as for implementing digital closed loop mode for maintaining the output voltage of all power supplies controlled by the monitoring and trimming section of the Platform Manager device. The FPGA section of the Platform Manager is optimized to meet the requirements of board management functions including reset distribution, boundary scan management, fault logging, FPGA load control, and system bus inter- face. The FPGA section uses look-up tables (LUTs) and distributed memories for flexible and efficient logic imple- mentation. This instant-on capability enables the Platform Manager devices to integrate control functions that are required as soon as power is applied to the board. Power management functions can be integrated into the CPLD and digital board management functions can be integrated into the FPGA using the LogiBuilder tool provided by PAC-Designer software. In addition, the FPGA designs can also be implemented in VHDL or Verilog HDL through the ispLEVER software design tool. 2 The Platform Manager IC supports a hardware I C/SMBus slave interface that can be used to measure voltages through the Analog to Digital Converter or is used for trimming and margining using a microcontroller. There are two JTAG ports integrated into the Platform Manager device: Power JTAG and FPGA JTAG. The Power JTAG interface is used to program the power section of the Platform Manager and the FPGA JTAG is used to con- figure the FPGA portion of the device. The FPGA configuration memory can be changed in-system without inter- rupting the operation of the board management section. However, the Power Management section of the platform Manager cannot be changed without interrupting the power management operation. Table 1. Platform Manager Family Selection Table Parameter LPTM10-1247 LPTM10-12107 Analog Inputs 12 12 Margin and Trim 6 8 Total I/O 47 107 CPLD Macrocells 48 48 FPGA LUTs 640 640 Package 128-pin TQFP 208-ball ftBGA 2