Product Information

LFE3-70EA-6FN484C

Product Image X-ON

Datasheet
FPGA - Field Programmable Gate Array 66.5K LUTs 295 IO SERDES 1.2V -6 Speed
Manufacturer: Lattice



Price (Ex GST)

From 96.3158

40 - Global Stock
Ships to you between
Thu. 22 Apr to Mon. 26 Apr

MOQ: 1 Multiples:1
Pack Size :   1
Availability Price Quantity
32 - Global Stock


Ships to you between Fri. 16 Apr to Thu. 22 Apr

MOQ : 1
Multiples : 1
1 : $ 145.3264

Buy
40 - Global Stock


Ships to you between Thu. 22 Apr to Mon. 26 Apr

MOQ : 1
Multiples : 1
1 : $ 103.2158
25 : $ 96.3158
100 : $ 96.3158

Buy
   
Manufacturer
Lattice
Product Category
FPGA - Field Programmable Gate Array
RoHS - XON
Y Icon ROHS
Product
Ecp3
Number of Logic Elements
67000
Number of Logic Array Blocks - LABs
8375
Total Memory
4565 Kbit
Number of I/Os
295 I/O
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+70 C
Mounting Style
Smd/Smt
Package / Case
FPBGA-484
Packaging
Tray
Series
Lfe3-70Ea-6Fn
Brand
Lattice
Distributed Ram
145 Kbit
Embedded Block Ram - Ebr
4420 Kbit
Maximum Operating Frequency
375 Mhz
Minimum Operating Temperature
0 C
Operating Supply Current
18 mA
Factory Pack Quantity :
60
LoadingGif
Image
Mfr. Part No.
Description
Stock
FPGA LatticeECP3 Family 67000 Cells 65nm Technology 1.2V 672-Pin FBGA
9
FPGA - Field Programmable Gate Array 66.5K LUTs 380 I/O SERDES 1.2V -6 Speed
40
FPGA - Field Programmable Gate Array 66.5K LUTs 295 IO SERDES 1.2V -7 Speed
10
Image
Mfr. Part No.
Description
Stock
FPGA LatticeECP3 Family 67000 Cells 65nm Technology 1.2V 672-Pin FBGA
9
FPGA - Field Programmable Gate Array 66.5K LUTs 380 I/O SERDES 1.2V -8 Speed
58

LatticeECP3 Family Data Sheet Preliminary DS1021 Version 01.6, March 2010LatticeECP3 Family Data Sheet Preliminary DS1021 Version 01.6, March 2010LatticeECP3 Family Data Sheet Introduction November 2009 Preliminary Data Sheet DS1021 ? Dedicated read/write levelling functionality Features ? Dedicated gearing logic ? Higher Logic Density for Increased System ? Source synchronous standards support Integration ? ADC/DAC, 7:1 LVDS, XGMII ? 17K to 149K LUTs ? High Speed ADC/DAC devices ? 133 to 586 I/Os ? Dedicated DDR/DDR2/DDR3 memory with DQS ? Embedded SERDES support ? 150 Mbps to 3.2 Gbps for Generic 8b10b, 10-bit ? Optional Inter-Symbol Interference (ISI) ? SERDES, and 8-bit SERDES modes correction on outputs ? Data Rates 230 Mbps to 3.2 Gbps per channel ? Programmable sysI/O? Buffer Supports for all other protocols Wide Range of Interfaces ? Up to 16 channels per device: PCI Express, ? On-chip termination SONET/SDH, Ethernet (1GbE, SGMII, XAUI), ? Optional equalization filter on inputs CPRI, SMPTE 3G and Serial RapidIO ? LVTTL and LVCMOS 33/25/18/15/12 ? sysDSP? ? SSTL 33/25/18/15 I, II ? Fully cascadable slice architecture ? HSTL15 I and HSTL18 I, II ? 12 to 160 slices for high performance multiply ? PCI and Differential HSTL, SSTL and accumulate ? LVDS, Bus-LVDS, LVPECL, RSDS, MLVDS ? Powerful 54-bit ALU operations ? Flexible Device Configuration ? Time Division Multiplexing MAC Sharing ? Dedicated bank for configuration I/Os ? Rounding and truncation ? SPI boot flash interface ? Each slice supports ? Dual-boot images supported ? Half 36x36, two 18x18 or four 9x9 multipliers ? Slave SPI ? Advanced 18x36 MAC and 18x18 Multiply-? ? TransFR? I/O for simple field updates Multiply-Accumulate (MMAC) operations ? Soft Error Detect embedded macro ? Flexible Memory Resources ? System Level Support ? Up to 6.85Mbits sysMEM? Embedded Block ? IEEE 1149.1 and IEEE 1532 compliant RAM (EBR) ? Reveal Logic Analyzer ? 36K to 303K bits distributed RAM ? ORCAstra FPGA configuration utility ? sysCLOCK Analog PLLs and DLLs ? On-chip oscillator for initialization & general use ? Two DLLs and up to ten PLLs per device ? 1.2V core power supply ? Pre-Engineered Source Synchronous I/O ? DDR registers in I/O cells Table 1-1. LatticeECP3? Family Selection Guide Device ECP3-17ECP3-35ECP3-70ECP3-95ECP3-150 LUTs (K) 17336792 149 sysMEM Blocks (18Kbits) 38 72 240 240 372 Embedded Memory (Kbits) 700 1327 4420 4420 6850 Distributed RAM Bits (Kbits) 36 68 145 188 303 18X18 Multipliers 24 64 128 128 320 SERDES (Quad) 11334 PLLs/DLLs 2 / 2 4 / 2 10 / 2 10 / 2 10 / 2 Packages and SERDES Channels/ I/O Combinations 256 ftBGA (17x17 mm) 4 / 133 4 / 133 484 fpBGA (23x23 mm) 4 / 222 4 / 295 4 / 295 4 / 295 672 fpBGA (27x27 mm) 4 / 310 8 / 380 8 / 380 8 / 380 1156 fpBGA (35x35 mm) 12 / 490 12 / 490 16 / 586 ? 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1-1 DS1021 Introduction_01.3LatticeECP3 Family Data Sheet Preliminary DS1021 Version 01.6, March 2010LatticeECP3 Family Data Sheet Preliminary DS1021 Version 01.6, March 2010LatticeECP3 Family Data Sheet Introduction November 2009 Preliminary Data Sheet DS1021 ? Dedicated read/write levelling functionality Features ? Dedicated gearing logic ? Higher Logic Density for Increased System ? Source synchronous standards support Integration ? ADC/DAC, 7:1 LVDS, XGMII ? 17K to 149K LUTs ? High Speed ADC/DAC devices ? 133 to 586 I/Os ? Dedicated DDR/DDR2/DDR3 memory with DQS ? Embedded SERDES support ? 150 Mbps to 3.2 Gbps for Generic 8b10b, 10-bit ? Optional Inter-Symbol Interference (ISI) ? SERDES, and 8-bit SERDES modes correction on outputs ? Data Rates 230 Mbps to 3.2 Gbps per channel ? Programmable sysI/O? Buffer Supports for all other protocols Wide Range of Interfaces ? Up to 16 channels per device: PCI Express, ? On-chip termination SONET/SDH, Ethernet (1GbE, SGMII, XAUI), ? Optional equalization filter on inputs CPRI, SMPTE 3G and Serial RapidIO ? LVTTL and LVCMOS 33/25/18/15/12 ? sysDSP? ? SSTL 33/25/18/15 I, II ? Fully cascadable slice architecture ? HSTL15 I and HSTL18 I, II ? 12 to 160 slices for high performance multiply ? PCI and Differential HSTL, SSTL and accumulate ? LVDS, Bus-LVDS, LVPECL, RSDS, MLVDS ? Powerful 54-bit ALU operations ? Flexible Device Configuration ? Time Division Multiplexing MAC Sharing ? Dedicated bank for configuration I/Os ? Rounding and truncation ? SPI boot flash interface ? Each slice supports ? Dual-boot images supported ? Half 36x36, two 18x18 or four 9x9 multipliers ? Slave SPI ? Advanced 18x36 MAC and 18x18 Multiply-? ? TransFR? I/O for simple field updates Multiply-Accumulate (MMAC) operations ? Soft Error Detect embedded macro ? Flexible Memory Resources ? System Level Support ? Up to 6.85Mbits sysMEM? Embedded Block ? IEEE 1149.1 and IEEE 1532 compliant RAM (EBR) ? Reveal Logic Analyzer ? 36K to 303K bits distributed RAM ? ORCAstra FPGA configuration utility ? sysCLOCK Analog PLLs and DLLs ? On-chip oscillator for initialization & general use ? Two DLLs and up to ten PLLs per device ? 1.2V core power supply ? Pre-Engineered Source Synchronous I/O ? DDR registers in I/O cells Table 1-1. LatticeECP3? Family Selection Guide Device ECP3-17ECP3-35ECP3-70ECP3-95ECP3-150 LUTs (K) 17336792 149 sysMEM Blocks (18Kbits) 38 72 240 240 372 Embedded Memory (Kbits) 700 1327 4420 4420 6850 Distributed RAM Bits (Kbits) 36 68 145 188 303 18X18 Multipliers 24 64 128 128 320 SERDES (Quad) 11334 PLLs/DLLs 2 / 2 4 / 2 10 / 2 10 / 2 10 / 2 Packages and SERDES Channels/ I/O Combinations 256 ftBGA (17x17 mm) 4 / 133 4 / 133 484 fpBGA (23x23 mm) 4 / 222 4 / 295 4 / 295 4 / 295 672 fpBGA (27x27 mm) 4 / 310 8 / 380 8 / 380 8 / 380 1156 fpBGA (35x35 mm) 12 / 490 12 / 490 16 / 586 ? 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1-1 DS1021 Introduction_01.3Introduction Lattice Semiconductor LatticeECP3 Family Data Sheet Introduction The LatticeECP3? (EConomy Plus Third generation) family of FPGA devices is optimized to deliver high perfor- mance features such as an enhanced DSP architecture, high speed SERDES and high speed source synchronous interfaces in an economical FPGA fabric. This combination is achieved through advances in device architecture and the use of 65nm technology making the devices suitable for high-volume, high-speed, low-cost applications. The LatticeECP3 device family expands look-up-table (LUT) capacity to 149K logic elements and supports up to 486 user I/Os. The LatticeECP3 device family also offers up to 320 18x18 multipliers and a wide range of parallel I/O standards. The LatticeECP3 FPGA fabric is optimized with high performance and low cost in mind. The LatticeECP3 devices utilize reconfigurable SRAM logic technology and provide popular building blocks such as LUT-based logic, distrib- uted and embedded memory, Phase Locked Loops (PLLs), Delay Locked Loops (DLLs), pre-engineered source synchronous I/O support, enhanced sysDSP slices and advanced configuration support, including encryption and dual-boot capabilities. The pre-engineered source synchronous logic implemented in the LatticeECP3 device family supports a broad range of interface standards, including DDR3, XGMII and 7:1 LVDS. The LatticeECP3 device family also features high speed SERDES with dedicated PCS functions. High jitter toler- ance and low transmit jitter allow the SERDES plus PCS blocks to be configured to support an array of popular data protocols including PCI Express, SMPTE, Ethernet (XAUI, GbE, and SGMII) and CPRI. Transmit Pre-empha- sis and Receive Equalization settings make the SERDES suitable for transmission and reception over various forms of media. The LatticeECP3 devices also provide flexible, reliable and secure configuration options, such as dual-boot capa- bility, bit-stream encryption, and TransFR field upgrade features. ? The ispLEVER design tool suite from Lattice allows large complex designs to be efficiently implemented using the LatticeECP3 FPGA family. Synthesis library support for LatticeECP3 is available for popular logic synthesis tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the LatticeECP3 device. The ispLEVER tool extracts the timing from the routing and back- annotates it into the design for timing verification. Lattice provides many pre-engineered IP (Intellectual Property) ispLeverCORE? modules for the LatticeECP3 family. By using these configurable soft core IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity. 1-2LatticeECP3 Family Data Sheet Preliminary DS1021 Version 01.6, March 2010LatticeECP3 Family Data Sheet Preliminary DS1021 Version 01.6, March 2010LatticeECP3 Family Data Sheet Introduction November 2009 Preliminary Data Sheet DS1021 ? Dedicated read/write levelling functionality Features ? Dedicated gearing logic ? Higher Logic Density for Increased System ? Source synchronous standards support Integration ? ADC/DAC, 7:1 LVDS, XGMII ? 17K to 149K LUTs ? High Speed ADC/DAC devices ? 133 to 586 I/Os ? Dedicated DDR/DDR2/DDR3 memory with DQS ? Embedded SERDES support ? 150 Mbps to 3.2 Gbps for Generic 8b10b, 10-bit ? Optional Inter-Symbol Interference (ISI) ? SERDES, and 8-bit SERDES modes correction on outputs ? Data Rates 230 Mbps to 3.2 Gbps per channel ? Programmable sysI/O? Buffer Supports for all other protocols Wide Range of Interfaces ? Up to 16 channels per device: PCI Express, ? On-chip termination SONET/SDH, Ethernet (1GbE, SGMII, XAUI), ? Optional equalization filter on inputs CPRI, SMPTE 3G and Serial RapidIO ? LVTTL and LVCMOS 33/25/18/15/12 ? sysDSP? ? SSTL 33/25/18/15 I, II ? Fully cascadable slice architecture ? HSTL15 I and HSTL18 I, II ? 12 to 160 slices for high performance multiply ? PCI and Differential HSTL, SSTL and accumulate ? LVDS, Bus-LVDS, LVPECL, RSDS, MLVDS ? Powerful 54-bit ALU operations ? Flexible Device Configuration ? Time Division Multiplexing MAC Sharing ? Dedicated bank for configuration I/Os ? Rounding and truncation ? SPI boot flash interface ? Each slice supports ? Dual-boot images supported ? Half 36x36, two 18x18 or four 9x9 multipliers ? Slave SPI ? Advanced 18x36 MAC and 18x18 Multiply-? ? TransFR? I/O for simple field updates Multiply-Accumulate (MMAC) operations ? Soft Error Detect embedded macro ? Flexible Memory Resources ? System Level Support ? Up to 6.85Mbits sysMEM? Embedded Block ? IEEE 1149.1 and IEEE 1532 compliant RAM (EBR) ? Reveal Logic Analyzer ? 36K to 303K bits distributed RAM ? ORCAstra FPGA configuration utility ? sysCLOCK Analog PLLs and DLLs ? On-chip oscillator for initialization & general use ? Two DLLs and up to ten PLLs per device ? 1.2V core power supply ? Pre-Engineered Source Synchronous I/O ? DDR registers in I/O cells Table 1-1. LatticeECP3? Family Selection Guide Device ECP3-17ECP3-35ECP3-70ECP3-95ECP3-150 LUTs (K) 17336792 149 sysMEM Blocks (18Kbits) 38 72 240 240 372 Embedded Memory (Kbits) 700 1327 4420 4420 6850 Distributed RAM Bits (Kbits) 36 68 145 188 303 18X18 Multipliers 24 64 128 128 320 SERDES (Quad) 11334 PLLs/DLLs 2 / 2 4 / 2 10 / 2 10 / 2 10 / 2 Packages and SERDES Channels/ I/O Combinations 256 ftBGA (17x17 mm) 4 / 133 4 / 133 484 fpBGA (23x23 mm) 4 / 222 4 / 295 4 / 295 4 / 295 672 fpBGA (27x27 mm) 4 / 310 8 / 380 8 / 380 8 / 380 1156 fpBGA (35x35 mm) 12 / 490 12 / 490 16 / 586 ? 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1-1 DS1021 Introduction_01.3LatticeECP3 Family Data Sheet Preliminary DS1021 Version 01.6, March 2010LatticeECP3 Family Data Sheet Preliminary DS1021 Version 01.6, March 2010LatticeECP3 Family Data Sheet Introduction November 2009 Preliminary Data Sheet DS1021 ? Dedicated read/write levelling functionality Features ? Dedicated gearing logic ? Higher Logic Density for Increased System ? Source synchronous standards support Integration ? ADC/DAC, 7:1 LVDS, XGMII ? 17K to 149K LUTs ? High Speed ADC/DAC devices ? 133 to 586 I/Os ? Dedicated DDR/DDR2/DDR3 memory with DQS ? Embedded SERDES support ? 150 Mbps to 3.2 Gbps for Generic 8b10b, 10-bit ? Optional Inter-Symbol Interference (ISI) ? SERDES, and 8-bit SERDES modes correction on outputs ? Data Rates 230 Mbps to 3.2 Gbps per channel ? Programmable sysI/O? Buffer Supports for all other protocols Wide Range of Interfaces ? Up to 16 channels per device: PCI Express, ? On-chip termination SONET/SDH, Ethernet (1GbE, SGMII, XAUI), ? Optional equalization filter on inputs CPRI, SMPTE 3G and Serial RapidIO ? LVTTL and LVCMOS 33/25/18/15/12 ? sysDSP? ? SSTL 33/25/18/15 I, II ? Fully cascadable slice architecture ? HSTL15 I and HSTL18 I, II ? 12 to 160 slices for high performance multiply ? PCI and Differential HSTL, SSTL and accumulate ? LVDS, Bus-LVDS, LVPECL, RSDS, MLVDS ? Powerful 54-bit ALU operations ? Flexible Device Configuration ? Time Division Multiplexing MAC Sharing ? Dedicated bank for configuration I/Os ? Rounding and truncation ? SPI boot flash interface ? Each slice supports ? Dual-boot images supported ? Half 36x36, two 18x18 or four 9x9 multipliers ? Slave SPI ? Advanced 18x36 MAC and 18x18 Multiply-? ? TransFR? I/O for simple field updates Multiply-Accumulate (MMAC) operations ? Soft Error Detect embedded macro ? Flexible Memory Resources ? System Level Support ? Up to 6.85Mbits sysMEM? Embedded Block ? IEEE 1149.1 and IEEE 1532 compliant RAM (EBR) ? Reveal Logic Analyzer ? 36K to 303K bits distributed RAM ? ORCAstra FPGA configuration utility ? sysCLOCK Analog PLLs and DLLs ? On-chip oscillator for initialization & general use ? Two DLLs and up to ten PLLs per device ? 1.2V core power supply ? Pre-Engineered Source Synchronous I/O ? DDR registers in I/O cells Table 1-1. LatticeECP3? Family Selection Guide Device ECP3-17ECP3-35ECP3-70ECP3-95ECP3-150 LUTs (K) 17336792 149 sysMEM Blocks (18Kbits) 38 72 240 240 372 Embedded Memory (Kbits) 700 1327 4420 4420 6850 Distributed RAM Bits (Kbits) 36 68 145 188 303 18X18 Multipliers 24 64 128 128 320 SERDES (Quad) 11334 PLLs/DLLs 2 / 2 4 / 2 10 / 2 10 / 2 10 / 2 Packages and SERDES Channels/ I/O Combinations 256 ftBGA (17x17 mm) 4 / 133 4 / 133 484 fpBGA (23x23 mm) 4 / 222 4 / 295 4 / 295 4 / 295 672 fpBGA (27x27 mm) 4 / 310 8 / 380 8 / 380 8 / 380 1156 fpBGA (35x35 mm) 12 / 490 12 / 490 16 / 586 ? 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1-1 DS1021 Introduction_01.3Introduction Lattice Semiconductor LatticeECP3 Family Data Sheet Introduction The LatticeECP3? (EConomy Plus Third generation) family of FPGA devices is optimized to deliver high perfor- mance features such as an enhanced DSP architecture, high speed SERDES and high speed source synchronous interfaces in an economical FPGA fabric. This combination is achieved through advances in device architecture and the use of 65nm technology making the devices suitable for high-volume, high-speed, low-cost applications. The LatticeECP3 device family expands look-up-table (LUT) capacity to 149K logic elements and supports up to 486 user I/Os. The LatticeECP3 device family also offers up to 320 18x18 multipliers and a wide range of parallel I/O standards. The LatticeECP3 FPGA fabric is optimized with high performance and low cost in mind. The LatticeECP3 devices utilize reconfigurable SRAM logic technology and provide popular building blocks such as LUT-based logic, distrib- uted and embedded memory, Phase Locked Loops (PLLs), Delay Locked Loops (DLLs), pre-engineered source synchronous I/O support, enhanced sysDSP slices and advanced configuration support, including encryption and dual-boot capabilities. The pre-engineered source synchronous logic implemented in the LatticeECP3 device family supports a broad range of interface standards, including DDR3, XGMII and 7:1 LVDS. The LatticeECP3 device family also features high speed SERDES with dedicated PCS functions. High jitter toler- ance and low transmit jitter allow the SERDES plus PCS blocks to be configured to support an array of popular data protocols including PCI Express, SMPTE, Ethernet (XAUI, GbE, and SGMII) and CPRI. Transmit Pre-empha- sis and Receive Equalization settings make the SERDES suitable for transmission and reception over various forms of media. The LatticeECP3 devices also provide flexible, reliable and secure configuration options, such as dual-boot capa- bility, bit-stream encryption, and TransFR field upgrade features. ? The ispLEVER design tool suite from Lattice allows large complex designs to be efficiently implemented using the LatticeECP3 FPGA family. Synthesis library support for LatticeECP3 is available for popular logic synthesis tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the LatticeECP3 device. The ispLEVER tool extracts the timing from the routing and back- annotates it into the design for timing verification. Lattice provides many pre-engineered IP (Intellectual Property) ispLeverCORE? modules for the LatticeECP3 family. By using these configurable soft core IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity. 1-2

Tariff Concession Code
Tariff Desc

Free
8542.31.00 51 No ..Application Specific (Digital) Integrated Circuits (ASIC)

Electronic integrated circuits: Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Monolithic integrated circuits:
LA4
LAT
LATTICE SEMI
Lattice Semiconductor
Lattice Semiconductor Corporation