LC4256V-3TN176C

? ispMACH 4000ZE Family 1.8V In-System Programmable Ultra Low Power PLDs August 2013 Data Sheet DS1022 ? Broad Device Offering Features ? 32 to 256 macrocells ? High Performance ? Multiple temperature range support ?f = 260MHz maximum operating frequency MAX ? Commercial: 0 to 90?C junction (T ) j ?t = 4.4ns propagation delay PD ? Industrial: -40 to 105?C junction (T ) j ? Up to four global clock pins with programmable ? Space-saving ucBGA and csBGA packages* clock polarity control ? Easy System Integration ? Up to 80 PTs per output ? Operation with 3.3V, 2.5V, 1.8V or 1.5V ? Ease of Design LVCMOS I/O ? Flexible CPLD macrocells with individual clock, ? 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI reset, preset and clock enable controls interfaces ? Up to four global OE controls ? Hot-socketing support ? Individual local OE control per I/O pin ? Open-drain output option TM ? Excellent First-Time-Fit and refit ? Programmable output slew rate ? Wide input gating (36 input logic blocks) for fast ? 3.3V PCI compatible counters, state machines and address decoders ? I/O pins with fast setup path ? Input hysteresis* ? Ultra Low Power ? 1.8V core power supply ? Standby current as low as 10?A typical ? IEEE 1149.1 boundary scan testable ? 1.8V core; low dynamic power ? IEEE 1532 ISC compliant ? Operational down to 1.6V V CC ? 1.8V In-System Programmable (ISP?) using ? Superior solution for power sensitive consumer Boundary Scan Test Access Port (TAP) applications ? Pb-free package options (only) ? Per pin pull-up, pull-down or bus keeper ? On-chip user oscillator and timer* control* ? Power Guard with multiple enable signals* *New enhanced features over original ispMACH 4000Z Table 1. ispMACH 4000ZE Family Selection Guide ispMACH 4032ZE ispMACH 4064ZE ispMACH 4128ZE ispMACH 4256ZE Macrocells 32 64 128 256 t (ns) 4.4 4.7 5.8 5.8 PD t (ns) 2.2 2.5 2.9 2.9 S t (ns) 3.0 3.2 3.8 3.8 CO f (MHz) 260 241 200 200 MAX Supply Voltages (V) 1.8V 1.8V 1.8V 1.8V 1 Packages (I/O + Dedicated Inputs) 48-Pin TQFP (7 x 7mm) 32+4 32+4 64-Ball csBGA (5 x 5mm) 32+4 48+4 64-Ball ucBGA (4 x 4mm) 48+4 100-Pin TQFP (14 x 14mm) 64+10 64+10 64+10 132-Ball ucBGA (6 x 6mm) 96+4 144-Pin TQFP (20 x 20mm) 96+4 96+14 144-Ball csBGA (7 x 7mm) 64+10 96+4 108+4 1. Pb-free only. ? 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 DS1022_01.8? ispMACH 4000ZE Family 1.8V In-System Programmable Ultra Low Power PLDs August 2013 Data Sheet DS1022 ? Broad Device Offering Features ? 32 to 256 macrocells ? High Performance ? Multiple temperature range support ?f = 260MHz maximum operating frequency MAX ? Commercial: 0 to 90?C junction (T ) j ?t = 4.4ns propagation delay PD ? Industrial: -40 to 105?C junction (T ) j ? Up to four global clock pins with programmable ? Space-saving ucBGA and csBGA packages* clock polarity control ? Easy System Integration ? Up to 80 PTs per output ? Operation with 3.3V, 2.5V, 1.8V or 1.5V ? Ease of Design LVCMOS I/O ? Flexible CPLD macrocells with individual clock, ? 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI reset, preset and clock enable controls interfaces ? Up to four global OE controls ? Hot-socketing support ? Individual local OE control per I/O pin ? Open-drain output option TM ? Excellent First-Time-Fit and refit ? Programmable output slew rate ? Wide input gating (36 input logic blocks) for fast ? 3.3V PCI compatible counters, state machines and address decoders ? I/O pins with fast setup path ? Input hysteresis* ? Ultra Low Power ? 1.8V core power supply ? Standby current as low as 10?A typical ? IEEE 1149.1 boundary scan testable ? 1.8V core; low dynamic power ? IEEE 1532 ISC compliant ? Operational down to 1.6V V CC ? 1.8V In-System Programmable (ISP?) using ? Superior solution for power sensitive consumer Boundary Scan Test Access Port (TAP) applications ? Pb-free package options (only) ? Per pin pull-up, pull-down or bus keeper ? On-chip user oscillator and timer* control* ? Power Guard with multiple enable signals* *New enhanced features over original ispMACH 4000Z Table 1. ispMACH 4000ZE Family Selection Guide ispMACH 4032ZE ispMACH 4064ZE ispMACH 4128ZE ispMACH 4256ZE Macrocells 32 64 128 256 t (ns) 4.4 4.7 5.8 5.8 PD t (ns) 2.2 2.5 2.9 2.9 S t (ns) 3.0 3.2 3.8 3.8 CO f (MHz) 260 241 200 200 MAX Supply Voltages (V) 1.8V 1.8V 1.8V 1.8V 1 Packages (I/O + Dedicated Inputs) 48-Pin TQFP (7 x 7mm) 32+4 32+4 64-Ball csBGA (5 x 5mm) 32+4 48+4 64-Ball ucBGA (4 x 4mm) 48+4 100-Pin TQFP (14 x 14mm) 64+10 64+10 64+10 132-Ball ucBGA (6 x 6mm) 96+4 144-Pin TQFP (20 x 20mm) 96+4 96+14 144-Ball csBGA (7 x 7mm) 64+10 96+4 108+4 1. Pb-free only. ? 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 DS1022_01.8ispMACH 4000ZE Family Data Sheet Introduction The high performance ispMACH 4000ZE family from Lattice offers an ultra low power CPLD solution. The new fam- ily is based on Lattice?s industry-leading ispMACH 4000 architecture. Retaining the best of the previous generation, the ispMACH 4000ZE architecture focuses on significant innovations to combine high performance with low power in a flexible CPLD family. For example, the family?s new Power Guard feature minimizes dynamic power consump- tion by preventing internal logic toggling due to unnecessary I/O pin activity. The ispMACH 4000ZE combines high speed and low power with the flexibility needed for ease of design. With its robust Global Routing Pool and Output Routing Pool, this family delivers excellent First-Time-Fit, timing predictabil- ity, routing, pin-out retention and density migration. The ispMACH 4000ZE family offers densities ranging from 32 to 256 macrocells. There are multiple density-I/O combinations in Thin Quad Flat Pack (TQFP), Chip Scale BGA (csBGA), and Ultra Chip Scale BGA (ucBGA) pack- ages ranging from 32 to 144 pins/balls. Table 1 shows the macrocell, package and I/O options, along with other key parameters. A user programmable internal oscillator and a timer are included in the device for tasks like LED control, keyboard scanner and similar housekeeping type state machines. This feature can be optionally disabled to save power. The ispMACH 4000ZE family has enhanced system integration capabilities. It supports a 1.8V supply voltage and 3.3V, 2.5V, 1.8V and 1.5V interface voltages. Additionally, inputs can be safely driven up to 5.5V when an I/O bank is configured for 3.3V operation, making this family 5V tolerant. The ispMACH 4000ZE also offers enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. Pull-up, pull-down and bus-keeper features are controllable on a ?per-pin? basis. The ispMACH 4000ZE family members are 1.8V in-system programmable through the IEEE Standard 1532 interface. IEEE Standard 1149.1 boundary scan testing capability also allows product testing on automated test equipment. The 1532 interface signals TCK, TMS, TDI and TDO are referenced to V (logic core). CC Overview The ispMACH 4000ZE devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks (GLBs) intercon- nected by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O Blocks (IOBs), which contain multiple I/O cells. This architecture is shown in Figure 1. Figure 1. Functional Block Diagram OSC I/O I/O 16 16 Block Block Generic Generic ORP 16 16 ORP Logic Logic 36 36 Block Block I/O I/O 16 16 Block Block Generic Generic ORP 16 16 ORP Logic Logic 36 36 Block Block 2 I/O Bank 0 V CCO0 GND CLK0/I CLK1/I CLK2/I CLK3/I Global Routing Pool GOE0 GOE1 V CC GND TCK TMS TDI TDO V CCO1 GND I/O Bank 1? ispMACH 4000ZE Family 1.8V In-System Programmable Ultra Low Power PLDs August 2013 Data Sheet DS1022 ? Broad Device Offering Features ? 32 to 256 macrocells ? High Performance ? Multiple temperature range support ?f = 260MHz maximum operating frequency MAX ? Commercial: 0 to 90?C junction (T ) j ?t = 4.4ns propagation delay PD ? Industrial: -40 to 105?C junction (T ) j ? Up to four global clock pins with programmable ? Space-saving ucBGA and csBGA packages* clock polarity control ? Easy System Integration ? Up to 80 PTs per output ? Operation with 3.3V, 2.5V, 1.8V or 1.5V ? Ease of Design LVCMOS I/O ? Flexible CPLD macrocells with individual clock, ? 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI reset, preset and clock enable controls interfaces ? Up to four global OE controls ? Hot-socketing support ? Individual local OE control per I/O pin ? Open-drain output option TM ? Excellent First-Time-Fit and refit ? Programmable output slew rate ? Wide input gating (36 input logic blocks) for fast ? 3.3V PCI compatible counters, state machines and address decoders ? I/O pins with fast setup path ? Input hysteresis* ? Ultra Low Power ? 1.8V core power supply ? Standby current as low as 10?A typical ? IEEE 1149.1 boundary scan testable ? 1.8V core; low dynamic power ? IEEE 1532 ISC compliant ? Operational down to 1.6V V CC ? 1.8V In-System Programmable (ISP?) using ? Superior solution for power sensitive consumer Boundary Scan Test Access Port (TAP) applications ? Pb-free package options (only) ? Per pin pull-up, pull-down or bus keeper ? On-chip user oscillator and timer* control* ? Power Guard with multiple enable signals* *New enhanced features over original ispMACH 4000Z Table 1. ispMACH 4000ZE Family Selection Guide ispMACH 4032ZE ispMACH 4064ZE ispMACH 4128ZE ispMACH 4256ZE Macrocells 32 64 128 256 t (ns) 4.4 4.7 5.8 5.8 PD t (ns) 2.2 2.5 2.9 2.9 S t (ns) 3.0 3.2 3.8 3.8 CO f (MHz) 260 241 200 200 MAX Supply Voltages (V) 1.8V 1.8V 1.8V 1.8V 1 Packages (I/O + Dedicated Inputs) 48-Pin TQFP (7 x 7mm) 32+4 32+4 64-Ball csBGA (5 x 5mm) 32+4 48+4 64-Ball ucBGA (4 x 4mm) 48+4 100-Pin TQFP (14 x 14mm) 64+10 64+10 64+10 132-Ball ucBGA (6 x 6mm) 96+4 144-Pin TQFP (20 x 20mm) 96+4 96+14 144-Ball csBGA (7 x 7mm) 64+10 96+4 108+4 1. Pb-free only. ? 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 DS1022_01.8? ispMACH 4000ZE Family 1.8V In-System Programmable Ultra Low Power PLDs August 2013 Data Sheet DS1022 ? Broad Device Offering Features ? 32 to 256 macrocells ? High Performance ? Multiple temperature range support ?f = 260MHz maximum operating frequency MAX ? Commercial: 0 to 90?C junction (T ) j ?t = 4.4ns propagation delay PD ? Industrial: -40 to 105?C junction (T ) j ? Up to four global clock pins with programmable ? Space-saving ucBGA and csBGA packages* clock polarity control ? Easy System Integration ? Up to 80 PTs per output ? Operation with 3.3V, 2.5V, 1.8V or 1.5V ? Ease of Design LVCMOS I/O ? Flexible CPLD macrocells with individual clock, ? 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI reset, preset and clock enable controls interfaces ? Up to four global OE controls ? Hot-socketing support ? Individual local OE control per I/O pin ? Open-drain output option TM ? Excellent First-Time-Fit and refit ? Programmable output slew rate ? Wide input gating (36 input logic blocks) for fast ? 3.3V PCI compatible counters, state machines and address decoders ? I/O pins with fast setup path ? Input hysteresis* ? Ultra Low Power ? 1.8V core power supply ? Standby current as low as 10?A typical ? IEEE 1149.1 boundary scan testable ? 1.8V core; low dynamic power ? IEEE 1532 ISC compliant ? Operational down to 1.6V V CC ? 1.8V In-System Programmable (ISP?) using ? Superior solution for power sensitive consumer Boundary Scan Test Access Port (TAP) applications ? Pb-free package options (only) ? Per pin pull-up, pull-down or bus keeper ? On-chip user oscillator and timer* control* ? Power Guard with multiple enable signals* *New enhanced features over original ispMACH 4000Z Table 1. ispMACH 4000ZE Family Selection Guide ispMACH 4032ZE ispMACH 4064ZE ispMACH 4128ZE ispMACH 4256ZE Macrocells 32 64 128 256 t (ns) 4.4 4.7 5.8 5.8 PD t (ns) 2.2 2.5 2.9 2.9 S t (ns) 3.0 3.2 3.8 3.8 CO f (MHz) 260 241 200 200 MAX Supply Voltages (V) 1.8V 1.8V 1.8V 1.8V 1 Packages (I/O + Dedicated Inputs) 48-Pin TQFP (7 x 7mm) 32+4 32+4 64-Ball csBGA (5 x 5mm) 32+4 48+4 64-Ball ucBGA (4 x 4mm) 48+4 100-Pin TQFP (14 x 14mm) 64+10 64+10 64+10 132-Ball ucBGA (6 x 6mm) 96+4 144-Pin TQFP (20 x 20mm) 96+4 96+14 144-Ball csBGA (7 x 7mm) 64+10 96+4 108+4 1. Pb-free only. ? 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 DS1022_01.8ispMACH 4000ZE Family Data Sheet Introduction The high performance ispMACH 4000ZE family from Lattice offers an ultra low power CPLD solution. The new fam- ily is based on Lattice?s industry-leading ispMACH 4000 architecture. Retaining the best of the previous generation, the ispMACH 4000ZE architecture focuses on significant innovations to combine high performance with low power in a flexible CPLD family. For example, the family?s new Power Guard feature minimizes dynamic power consump- tion by preventing internal logic toggling due to unnecessary I/O pin activity. The ispMACH 4000ZE combines high speed and low power with the flexibility needed for ease of design. With its robust Global Routing Pool and Output Routing Pool, this family delivers excellent First-Time-Fit, timing predictabil- ity, routing, pin-out retention and density migration. The ispMACH 4000ZE family offers densities ranging from 32 to 256 macrocells. There are multiple density-I/O combinations in Thin Quad Flat Pack (TQFP), Chip Scale BGA (csBGA), and Ultra Chip Scale BGA (ucBGA) pack- ages ranging from 32 to 144 pins/balls. Table 1 shows the macrocell, package and I/O options, along with other key parameters. A user programmable internal oscillator and a timer are included in the device for tasks like LED control, keyboard scanner and similar housekeeping type state machines. This feature can be optionally disabled to save power. The ispMACH 4000ZE family has enhanced system integration capabilities. It supports a 1.8V supply voltage and 3.3V, 2.5V, 1.8V and 1.5V interface voltages. Additionally, inputs can be safely driven up to 5.5V when an I/O bank is configured for 3.3V operation, making this family 5V tolerant. The ispMACH 4000ZE also offers enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. Pull-up, pull-down and bus-keeper features are controllable on a ?per-pin? basis. The ispMACH 4000ZE family members are 1.8V in-system programmable through the IEEE Standard 1532 interface. IEEE Standard 1149.1 boundary scan testing capability also allows product testing on automated test equipment. The 1532 interface signals TCK, TMS, TDI and TDO are referenced to V (logic core). CC Overview The ispMACH 4000ZE devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks (GLBs) intercon- nected by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O Blocks (IOBs), which contain multiple I/O cells. This architecture is shown in Figure 1. Figure 1. Functional Block Diagram OSC I/O I/O 16 16 Block Block Generic Generic ORP 16 16 ORP Logic Logic 36 36 Block Block I/O I/O 16 16 Block Block Generic Generic ORP 16 16 ORP Logic Logic 36 36 Block Block 2 I/O Bank 0 V CCO0 GND CLK0/I CLK1/I CLK2/I CLK3/I Global Routing Pool GOE0 GOE1 V CC GND TCK TMS TDI TDO V CCO1 GND I/O Bank 1ispMACH 4000ZE Family Data Sheet The I/Os in the ispMACH 4000ZE are split into two banks. Each bank has a separate I/O power supply. Inputs can support a variety of standards independent of the chip or bank power supply. Outputs support the standards com- patible with the power supply provided to the bank. Support for a variety of standards helps designers implement designs in mixed voltage environments. In addition, 5V tolerant inputs are specified within an I/O bank that is con- nected to a V of 3.0V to 3.6V for LVCMOS 3.3, LVTTL and PCI interfaces. CCO Architecture There are a total of two GLBs in the ispMACH 4032ZE, increasing to 16 GLBs in the ispMACH 4256ZE. Each GLB has 36 inputs. All GLB inputs come from the GRP and all outputs from the GLB are brought back into the GRP to be connected to the inputs of any other GLB on the device. Even if feedback signals return to the same GLB, they still must go through the GRP. This mechanism ensures that GLBs communicate with each other with consistent and predictable delays. The outputs from the GLB are also sent to the ORP. The ORP then sends them to the asso- ciated I/O cells in the I/O block. Generic Logic Block The ispMACH 4000ZE GLB consists of a programmable AND array, logic allocator, 16 macrocells and a GLB clock generator. Macrocells are decoupled from the product terms through the logic allocator and the I/O pins are decou- pled from macrocells through the ORP. Figure 2 illustrates the GLB. Figure 2. Generic Logic Block To GRP Clock Generator 1+OE 1+OE 1+OE 1+OE 1+OE 36 Inputs from GRP 1+OE 1+OE 1+OE To Product Term Output Enable Sharing. Also, To Input Enable of Power Guard on I/Os in the block. AND Array The programmable AND Array consists of 36 inputs and 83 output product terms. The 36 inputs from the GRP are used to form 72 lines in the AND Array (true and complement of the inputs). Each line in the array can be con- nected to any of the 83 output product terms via a wired-AND. Each of the 80 logic product terms feed the logic allocator with the remaining three control product terms feeding the Shared PT Clock, Shared PT Initialization and Shared PT OE. The Shared PT Clock and Shared PT Initialization signals can optionally be inverted before being fed to the macrocells. Every set of five product terms from the 80 logic product terms forms a product term cluster starting with PT0. There is one product term cluster for every macrocell in the GLB. Figure 3 is a graphical representation of the AND Array. 3 AND Array 36 Inputs, 83 Product Terms CLK0 Logic Allocator CLK1 CLK2 CLK3 16 Macrocells 16 MC Feedback Signals To ORP? ispMACH 4000ZE Family 1.8V In-System Programmable Ultra Low Power PLDs August 2013 Data Sheet DS1022 ? Broad Device Offering Features ? 32 to 256 macrocells ? High Performance ? Multiple temperature range support ?f = 260MHz maximum operating frequency MAX ? Commercial: 0 to 90?C junction (T ) j ?t = 4.4ns propagation delay PD ? Industrial: -40 to 105?C junction (T ) j ? Up to four global clock pins with programmable ? Space-saving ucBGA and csBGA packages* clock polarity control ? Easy System Integration ? Up to 80 PTs per output ? Operation with 3.3V, 2.5V, 1.8V or 1.5V ? Ease of Design LVCMOS I/O ? Flexible CPLD macrocells with individual clock, ? 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI reset, preset and clock enable controls interfaces ? Up to four global OE controls ? Hot-socketing support ? Individual local OE control per I/O pin ? Open-drain output option TM ? Excellent First-Time-Fit and refit ? Programmable output slew rate ? Wide input gating (36 input logic blocks) for fast ? 3.3V PCI compatible counters, state machines and address decoders ? I/O pins with fast setup path ? Input hysteresis* ? Ultra Low Power ? 1.8V core power supply ? Standby current as low as 10?A typical ? IEEE 1149.1 boundary scan testable ? 1.8V core; low dynamic power ? IEEE 1532 ISC compliant ? Operational down to 1.6V V CC ? 1.8V In-System Programmable (ISP?) using ? Superior solution for power sensitive consumer Boundary Scan Test Access Port (TAP) applications ? Pb-free package options (only) ? Per pin pull-up, pull-down or bus keeper ? On-chip user oscillator and timer* control* ? Power Guard with multiple enable signals* *New enhanced features over original ispMACH 4000Z Table 1. ispMACH 4000ZE Family Selection Guide ispMACH 4032ZE ispMACH 4064ZE ispMACH 4128ZE ispMACH 4256ZE Macrocells 32 64 128 256 t (ns) 4.4 4.7 5.8 5.8 PD t (ns) 2.2 2.5 2.9 2.9 S t (ns) 3.0 3.2 3.8 3.8 CO f (MHz) 260 241 200 200 MAX Supply Voltages (V) 1.8V 1.8V 1.8V 1.8V 1 Packages (I/O + Dedicated Inputs) 48-Pin TQFP (7 x 7mm) 32+4 32+4 64-Ball csBGA (5 x 5mm) 32+4 48+4 64-Ball ucBGA (4 x 4mm) 48+4 100-Pin TQFP (14 x 14mm) 64+10 64+10 64+10 132-Ball ucBGA (6 x 6mm) 96+4 144-Pin TQFP (20 x 20mm) 96+4 96+14 144-Ball csBGA (7 x 7mm) 64+10 96+4 108+4 1. Pb-free only. ? 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 DS1022_01.8? ispMACH 4000ZE Family 1.8V In-System Programmable Ultra Low Power PLDs August 2013 Data Sheet DS1022 ? Broad Device Offering Features ? 32 to 256 macrocells ? High Performance ? Multiple temperature range support ?f = 260MHz maximum operating frequency MAX ? Commercial: 0 to 90?C junction (T ) j ?t = 4.4ns propagation delay PD ? Industrial: -40 to 105?C junction (T ) j ? Up to four global clock pins with programmable ? Space-saving ucBGA and csBGA packages* clock polarity control ? Easy System Integration ? Up to 80 PTs per output ? Operation with 3.3V, 2.5V, 1.8V or 1.5V ? Ease of Design LVCMOS I/O ? Flexible CPLD macrocells with individual clock, ? 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI reset, preset and clock enable controls interfaces ? Up to four global OE controls ? Hot-socketing support ? Individual local OE control per I/O pin ? Open-drain output option TM ? Excellent First-Time-Fit and refit ? Programmable output slew rate ? Wide input gating (36 input logic blocks) for fast ? 3.3V PCI compatible counters, state machines and address decoders ? I/O pins with fast setup path ? Input hysteresis* ? Ultra Low Power ? 1.8V core power supply ? Standby current as low as 10?A typical ? IEEE 1149.1 boundary scan testable ? 1.8V core; low dynamic power ? IEEE 1532 ISC compliant ? Operational down to 1.6V V CC ? 1.8V In-System Programmable (ISP?) using ? Superior solution for power sensitive consumer Boundary Scan Test Access Port (TAP) applications ? Pb-free package options (only) ? Per pin pull-up, pull-down or bus keeper ? On-chip user oscillator and timer* control* ? Power Guard with multiple enable signals* *New enhanced features over original ispMACH 4000Z Table 1. ispMACH 4000ZE Family Selection Guide ispMACH 4032ZE ispMACH 4064ZE ispMACH 4128ZE ispMACH 4256ZE Macrocells 32 64 128 256 t (ns) 4.4 4.7 5.8 5.8 PD t (ns) 2.2 2.5 2.9 2.9 S t (ns) 3.0 3.2 3.8 3.8 CO f (MHz) 260 241 200 200 MAX Supply Voltages (V) 1.8V 1.8V 1.8V 1.8V 1 Packages (I/O + Dedicated Inputs) 48-Pin TQFP (7 x 7mm) 32+4 32+4 64-Ball csBGA (5 x 5mm) 32+4 48+4 64-Ball ucBGA (4 x 4mm) 48+4 100-Pin TQFP (14 x 14mm) 64+10 64+10 64+10 132-Ball ucBGA (6 x 6mm) 96+4 144-Pin TQFP (20 x 20mm) 96+4 96+14 144-Ball csBGA (7 x 7mm) 64+10 96+4 108+4 1. Pb-free only. ? 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 DS1022_01.8ispMACH 4000ZE Family Data Sheet Introduction The high performance ispMACH 4000ZE family from Lattice offers an ultra low power CPLD solution. The new fam- ily is based on Lattice?s industry-leading ispMACH 4000 architecture. Retaining the best of the previous generation, the ispMACH 4000ZE architecture focuses on significant innovations to combine high performance with low power in a flexible CPLD family. For example, the family?s new Power Guard feature minimizes dynamic power consump- tion by preventing internal logic toggling due to unnecessary I/O pin activity. The ispMACH 4000ZE combines high speed and low power with the flexibility needed for ease of design. With its robust Global Routing Pool and Output Routing Pool, this family delivers excellent First-Time-Fit, timing predictabil- ity, routing, pin-out retention and density migration. The ispMACH 4000ZE family offers densities ranging from 32 to 256 macrocells. There are multiple density-I/O combinations in Thin Quad Flat Pack (TQFP), Chip Scale BGA (csBGA), and Ultra Chip Scale BGA (ucBGA) pack- ages ranging from 32 to 144 pins/balls. Table 1 shows the macrocell, package and I/O options, along with other key parameters. A user programmable internal oscillator and a timer are included in the device for tasks like LED control, keyboard scanner and similar housekeeping type state machines. This feature can be optionally disabled to save power. The ispMACH 4000ZE family has enhanced system integration capabilities. It supports a 1.8V supply voltage and 3.3V, 2.5V, 1.8V and 1.5V interface voltages. Additionally, inputs can be safely driven up to 5.5V when an I/O bank is configured for 3.3V operation, making this family 5V tolerant. The ispMACH 4000ZE also offers enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. Pull-up, pull-down and bus-keeper features are controllable on a ?per-pin? basis. The ispMACH 4000ZE family members are 1.8V in-system programmable through the IEEE Standard 1532 interface. IEEE Standard 1149.1 boundary scan testing capability also allows product testing on automated test equipment. The 1532 interface signals TCK, TMS, TDI and TDO are referenced to V (logic core). CC Overview The ispMACH 4000ZE devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks (GLBs) intercon- nected by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O Blocks (IOBs), which contain multiple I/O cells. This architecture is shown in Figure 1. Figure 1. Functional Block Diagram OSC I/O I/O 16 16 Block Block Generic Generic ORP 16 16 ORP Logic Logic 36 36 Block Block I/O I/O 16 16 Block Block Generic Generic ORP 16 16 ORP Logic Logic 36 36 Block Block 2 I/O Bank 0 V CCO0 GND CLK0/I CLK1/I CLK2/I CLK3/I Global Routing Pool GOE0 GOE1 V CC GND TCK TMS TDI TDO V CCO1 GND I/O Bank 1? ispMACH 4000ZE Family 1.8V In-System Programmable Ultra Low Power PLDs August 2013 Data Sheet DS1022 ? Broad Device Offering Features ? 32 to 256 macrocells ? High Performance ? Multiple temperature range support ?f = 260MHz maximum operating frequency MAX ? Commercial: 0 to 90?C junction (T ) j ?t = 4.4ns propagation delay PD ? Industrial: -40 to 105?C junction (T ) j ? Up to four global clock pins with programmable ? Space-saving ucBGA and csBGA packages* clock polarity control ? Easy System Integration ? Up to 80 PTs per output ? Operation with 3.3V, 2.5V, 1.8V or 1.5V ? Ease of Design LVCMOS I/O ? Flexible CPLD macrocells with individual clock, ? 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI reset, preset and clock enable controls interfaces ? Up to four global OE controls ? Hot-socketing support ? Individual local OE control per I/O pin ? Open-drain output option TM ? Excellent First-Time-Fit and refit ? Programmable output slew rate ? Wide input gating (36 input logic blocks) for fast ? 3.3V PCI compatible counters, state machines and address decoders ? I/O pins with fast setup path ? Input hysteresis* ? Ultra Low Power ? 1.8V core power supply ? Standby current as low as 10?A typical ? IEEE 1149.1 boundary scan testable ? 1.8V core; low dynamic power ? IEEE 1532 ISC compliant ? Operational down to 1.6V V CC ? 1.8V In-System Programmable (ISP?) using ? Superior solution for power sensitive consumer Boundary Scan Test Access Port (TAP) applications ? Pb-free package options (only) ? Per pin pull-up, pull-down or bus keeper ? On-chip user oscillator and timer* control* ? Power Guard with multiple enable signals* *New enhanced features over original ispMACH 4000Z Table 1. ispMACH 4000ZE Family Selection Guide ispMACH 4032ZE ispMACH 4064ZE ispMACH 4128ZE ispMACH 4256ZE Macrocells 32 64 128 256 t (ns) 4.4 4.7 5.8 5.8 PD t (ns) 2.2 2.5 2.9 2.9 S t (ns) 3.0 3.2 3.8 3.8 CO f (MHz) 260 241 200 200 MAX Supply Voltages (V) 1.8V 1.8V 1.8V 1.8V 1 Packages (I/O + Dedicated Inputs) 48-Pin TQFP (7 x 7mm) 32+4 32+4 64-Ball csBGA (5 x 5mm) 32+4 48+4 64-Ball ucBGA (4 x 4mm) 48+4 100-Pin TQFP (14 x 14mm) 64+10 64+10 64+10 132-Ball ucBGA (6 x 6mm) 96+4 144-Pin TQFP (20 x 20mm) 96+4 96+14 144-Ball csBGA (7 x 7mm) 64+10 96+4 108+4 1. Pb-free only. ? 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 DS1022_01.8? ispMACH 4000ZE Family 1.8V In-System Programmable Ultra Low Power PLDs August 2013 Data Sheet DS1022 ? Broad Device Offering Features ? 32 to 256 macrocells ? High Performance ? Multiple temperature range support ?f = 260MHz maximum operating frequency MAX ? Commercial: 0 to 90?C junction (T ) j ?t = 4.4ns propagation delay PD ? Industrial: -40 to 105?C junction (T ) j ? Up to four global clock pins with programmable ? Space-saving ucBGA and csBGA packages* clock polarity control ? Easy System Integration ? Up to 80 PTs per output ? Operation with 3.3V, 2.5V, 1.8V or 1.5V ? Ease of Design LVCMOS I/O ? Flexible CPLD macrocells with individual clock, ? 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI reset, preset and clock enable controls interfaces ? Up to four global OE controls ? Hot-socketing support ? Individual local OE control per I/O pin ? Open-drain output option TM ? Excellent First-Time-Fit and refit ? Programmable output slew rate ? Wide input gating (36 input logic blocks) for fast ? 3.3V PCI compatible counters, state machines and address decoders ? I/O pins with fast setup path ? Input hysteresis* ? Ultra Low Power ? 1.8V core power supply ? Standby current as low as 10?A typical ? IEEE 1149.1 boundary scan testable ? 1.8V core; low dynamic power ? IEEE 1532 ISC compliant ? Operational down to 1.6V V CC ? 1.8V In-System Programmable (ISP?) using ? Superior solution for power sensitive consumer Boundary Scan Test Access Port (TAP) applications ? Pb-free package options (only) ? Per pin pull-up, pull-down or bus keeper ? On-chip user oscillator and timer* control* ? Power Guard with multiple enable signals* *New enhanced features over original ispMACH 4000Z Table 1. ispMACH 4000ZE Family Selection Guide ispMACH 4032ZE ispMACH 4064ZE ispMACH 4128ZE ispMACH 4256ZE Macrocells 32 64 128 256 t (ns) 4.4 4.7 5.8 5.8 PD t (ns) 2.2 2.5 2.9 2.9 S t (ns) 3.0 3.2 3.8 3.8 CO f (MHz) 260 241 200 200 MAX Supply Voltages (V) 1.8V 1.8V 1.8V 1.8V 1 Packages (I/O + Dedicated Inputs) 48-Pin TQFP (7 x 7mm) 32+4 32+4 64-Ball csBGA (5 x 5mm) 32+4 48+4 64-Ball ucBGA (4 x 4mm) 48+4 100-Pin TQFP (14 x 14mm) 64+10 64+10 64+10 132-Ball ucBGA (6 x 6mm) 96+4 144-Pin TQFP (20 x 20mm) 96+4 96+14 144-Ball csBGA (7 x 7mm) 64+10 96+4 108+4 1. Pb-free only. ? 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 DS1022_01.8ispMACH 4000ZE Family Data Sheet Introduction The high performance ispMACH 4000ZE family from Lattice offers an ultra low power CPLD solution. The new fam- ily is based on Lattice?s industry-leading ispMACH 4000 architecture. Retaining the best of the previous generation, the ispMACH 4000ZE architecture focuses on significant innovations to combine high performance with low power in a flexible CPLD family. For example, the family?s new Power Guard feature minimizes dynamic power consump- tion by preventing internal logic toggling due to unnecessary I/O pin activity. The ispMACH 4000ZE combines high speed and low power with the flexibility needed for ease of design. With its robust Global Routing Pool and Output Routing Pool, this family delivers excellent First-Time-Fit, timing predictabil- ity, routing, pin-out retention and density migration. The ispMACH 4000ZE family offers densities ranging from 32 to 256 macrocells. There are multiple density-I/O combinations in Thin Quad Flat Pack (TQFP), Chip Scale BGA (csBGA), and Ultra Chip Scale BGA (ucBGA) pack- ages ranging from 32 to 144 pins/balls. Table 1 shows the macrocell, package and I/O options, along with other key parameters. A user programmable internal oscillator and a timer are included in the device for tasks like LED control, keyboard scanner and similar housekeeping type state machines. This feature can be optionally disabled to save power. The ispMACH 4000ZE family has enhanced system integration capabilities. It supports a 1.8V supply voltage and 3.3V, 2.5V, 1.8V and 1.5V interface voltages. Additionally, inputs can be safely driven up to 5.5V when an I/O bank is configured for 3.3V operation, making this family 5V tolerant. The ispMACH 4000ZE also offers enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. Pull-up, pull-down and bus-keeper features are controllable on a ?per-pin? basis. The ispMACH 4000ZE family members are 1.8V in-system programmable through the IEEE Standard 1532 interface. IEEE Standard 1149.1 boundary scan testing capability also allows product testing on automated test equipment. The 1532 interface signals TCK, TMS, TDI and TDO are referenced to V (logic core). CC Overview The ispMACH 4000ZE devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks (GLBs) intercon- nected by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O Blocks (IOBs), which contain multiple I/O cells. This architecture is shown in Figure 1. Figure 1. Functional Block Diagram OSC I/O I/O 16 16 Block Block Generic Generic ORP 16 16 ORP Logic Logic 36 36 Block Block I/O I/O 16 16 Block Block Generic Generic ORP 16 16 ORP Logic Logic 36 36 Block Block 2 I/O Bank 0 V CCO0 GND CLK0/I CLK1/I CLK2/I CLK3/I Global Routing Pool GOE0 GOE1 V CC GND TCK TMS TDI TDO V CCO1 GND I/O Bank 1ispMACH 4000ZE Family Data Sheet The I/Os in the ispMACH 4000ZE are split into two banks. Each bank has a separate I/O power supply. Inputs can support a variety of standards independent of the chip or bank power supply. Outputs support the standards com- patible with the power supply provided to the bank. Support for a variety of standards helps designers implement designs in mixed voltage environments. In addition, 5V tolerant inputs are specified within an I/O bank that is con- nected to a V of 3.0V to 3.6V for LVCMOS 3.3, LVTTL and PCI interfaces. CCO Architecture There are a total of two GLBs in the ispMACH 4032ZE, increasing to 16 GLBs in the ispMACH 4256ZE. Each GLB has 36 inputs. All GLB inputs come from the GRP and all outputs from the GLB are brought back into the GRP to be connected to the inputs of any other GLB on the device. Even if feedback signals return to the same GLB, they still must go through the GRP. This mechanism ensures that GLBs communicate with each other with consistent and predictable delays. The outputs from the GLB are also sent to the ORP. The ORP then sends them to the asso- ciated I/O cells in the I/O block. Generic Logic Block The ispMACH 4000ZE GLB consists of a programmable AND array, logic allocator, 16 macrocells and a GLB clock generator. Macrocells are decoupled from the product terms through the logic allocator and the I/O pins are decou- pled from macrocells through the ORP. Figure 2 illustrates the GLB. Figure 2. Generic Logic Block To GRP Clock Generator 1+OE 1+OE 1+OE 1+OE 1+OE 36 Inputs from GRP 1+OE 1+OE 1+OE To Product Term Output Enable Sharing. Also, To Input Enable of Power Guard on I/Os in the block. AND Array The programmable AND Array consists of 36 inputs and 83 output product terms. The 36 inputs from the GRP are used to form 72 lines in the AND Array (true and complement of the inputs). Each line in the array can be con- nected to any of the 83 output product terms via a wired-AND. Each of the 80 logic product terms feed the logic allocator with the remaining three control product terms feeding the Shared PT Clock, Shared PT Initialization and Shared PT OE. The Shared PT Clock and Shared PT Initialization signals can optionally be inverted before being fed to the macrocells. Every set of five product terms from the 80 logic product terms forms a product term cluster starting with PT0. There is one product term cluster for every macrocell in the GLB. Figure 3 is a graphical representation of the AND Array. 3 AND Array 36 Inputs, 83 Product Terms CLK0 Logic Allocator CLK1 CLK2 CLK3 16 Macrocells 16 MC Feedback Signals To ORP