Product Information

EPC2LC20

EPC2LC20 electronic component of Intel

Datasheet
FPGA - Configuration Memory IC - Ser. Config Mem Flash 1.6Mb 10 MHz

Manufacturer: Intel
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Price (USD)

1: USD 232.7622 ea
Line Total: USD 232.7622

1661 - Global Stock
Ships to you between
Thu. 04 Apr to Wed. 10 Apr
MOQ: 1  Multiples: 1
Pack Size: 1
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2068 - Global Stock


Ships to you between Thu. 04 Apr to Wed. 10 Apr

MOQ : 1
Multiples : 1

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EPC2LC20
Intel

1 : USD 222.3625
10 : USD 148.2375
50 : USD 127.0625
100 : USD 88.95
500 : USD 83.9125
1000 : USD 80.8625

     
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Configuration Devices for SRAM-Based LUT Devices CF52005-3.0 Datasheet This datasheet describes configuration devices for SRAM-based look-up table (LUT) devices. Supported Devices Table 1 lists the supported Altera configuration devices. Table 1. Altera Configuration Devices Cascaded Recommended Device Memory Size (Bits) ISP Support Reprogrammable Support Operating Voltage (V) EPC1 1,046,496 No Yes No 5.0 or 3.3 EPC2 1,695,680 Yes Yes Yes 5.0 or 3.3 EPC1064 65,536 No No No 5.0 EPC1064V 65,536 No No No 3.3 EPC1213 212,942 No Yes No 5.0 EPC1441 440,800 No No No 5.0 or 3.3 Features Configuration devices for SRAM-based LUT devices offer the following features: Configures Altera ACEX 1K, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arria GX, Cyclone , Cyclone II, FLEX 10K (including FLEX 10KE and FLEX 10KA) Mercury , Stratix , Stratix GX, Stratix II, and Stratix II GX devices Easy-to-use four-pin interface Low current during configuration and near-zero standby mode current Programming support with the Altera Programming Unit (APU) and programming hardware from Data I/O, BP Microsystems, and other third-party programmers Available in compact plastic packages 8-pin plastic dual in-line (PDIP) package 20-pin plastic J-lead chip carrier (PLCC) package 32-pin plastic thin quad flat pack (TQFP) package EPC2 device has reprogrammable flash configuration memory 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their ISO respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor 9001:2008 products to current specifications in accordance with Altera s standard warranty, but reserves the right to make changes to any 101 Innovation Drive Registered products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use San Jose, CA 95134 of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders www.altera.com for products or services. January 2012 Altera Corporation SubscribePage 2 Functional Description 5.0-V and 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1 Supports programming through Serial Vector Format File (.svf), Jam Standard Test and Programming Language (STAPL) Format File (.jam), JAM Byte Code File (.jbc), and the Quartus II and MAX+PLUS II softwares using the USB-Blaster , MasterBlaster , ByteBlaster II, EthernetBlaster, or ByteBlasterMV download cable Supports programming through Programmer Object File (.pof) for EPC1 and EPC1441 devices nINIT CONF pin allows INIT CONF JTAG instruction to begin FPGA configuration f For more information about enhanced configuration (EPC) devices, refer to the Enhanced Configuration (EPC) Devices Datasheet. f For more information about serial configuration (EPCS) devices, refer to the Serial Configuration (EPCS) Devices Datasheet. Functional Description With SRAM-based devices, configuration data must be reloaded each time the device powers up, the system initializes, or when new configuration data is needed. Altera configuration devices store configuration data for SRAM-based ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices. Table 2 lists the supported configuration devices required to configure the ACEX 1K, APEX 20K, APEX 20KC, APEX 20KE, APEX II, Cyclone, Cyclone II, FLEX 10K, FLEX 10KA, FLEX 10KE, FLEX 6000/A, FLEX 8000A, Mercury, Stratix, Stratix GX, or Stratix II device. Table 2. Supported Configuration Devices (Part 1 of 4) EPC1064 or Data Size (Bits) Device Family Device EPC1213 EPC1441 EPC1 EPC2 (1) EPC1064V EP1K10 159,160 1 1 1 EP1K30 473,720 1 1 ACEX 1K EP1K50 784,184 1 1 EP1K100 1,335,720 1 EP20K100 993,360 1 1 APEX 20K EP20K200 1,950,800 2 EP20K400 3,880,720 3 EP20K200C 1,968,016 2 EP20K400C 3,909,776 3 APEX 20KC EP20K600C 5,673,936 4 EP20K1000C 8,960,016 6 Configuration Devices for SRAM-Based LUT Devices January 2012 Altera Corporation

Tariff Desc

8542.31.00 51 No ..Application Specific (Digital) Integrated Circuits (ASIC)

Electronic integrated circuits: Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Monolithic integrated circuits:
ALTERA
Altera (part of the Intel Group)
Altera (VA)
Altera Corporation
INTEL (ALTERA)
Intel (CPU)
Intel (formerly Altera)
Intel / Altera
INTEL / LEVEL ONE

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