DATASHEET 19-OUTPUT DB1900Z LOW-POWER DERIVATIVE 9ZXL1930 Description Features/Benefits The 9ZXL1930 is a low power version of the Intel DB1900Z Fixed feedback path 0ps input-to-output delay Differential Buffer utilizing Low-Power HCSL (LP-HCSL) 9 Selectable SMBus addresses Multiple devices can outputs to reduce power consumption more than 50% from share same SMBus segment the original IDT9ZX21901. It is suitable for PCI-Express Separate VDDIO for outputs allows maximum power Gen1/2/3 or QPI/UPI applications, and uses a fixed external savings feedback to maintain low drift for demanding QPI/UPI applications. PLL or bypass mode PLL can dejitter incoming clock Selectable PLL BW minimizes jitter peaking in downstream PLL s Recommended Application Spread spectrum compatible tracks spreading input Buffer for Romley, Grantley and Purley Servers clock for EMI reduction SMBus Interface unused outputs can be disabled Key Specifications 100MHz & 133.33MHz PLL mode Legacy QPI/UPI Cycle-to-cycle jitter: < 50ps support Output-to-output skew: <85ps Differential outputs are Low/Low in power down Input-to-output delay: Fixed at 0 ps Maximum power savings Input-to-output delay variation: <50ps Phase jitter: PCIe Gen3 < 1ps rms Output Features Phase jitter: QPI/UPI 9.6GB/s < 0.2ps rms 19 - LP-HCSL Differential Output Pairs Block Diagram FBOUT NC Z-PLL (SS Compatible) DIF IN DIF18 DIF IN HIBW BYPM LOBW 100M 133M CKPWRGD/PD DIF0 SMB A0 tri Logic SMB A1 tri SMBDAT SMBCLK IDT 19-OUTPUT DB1900Z LOW-POWER DERIVATIVE 1 9ZXL1930 REV D 112015DIF 6 DIF 6 GND VDDIO DIF 5 DIF 5 DIF 4 DIF 4 VDD GND DIF 3 DIF 3 DIF 2 DIF 2 GND VDDIO DIF 1 DIF 1 9ZXL1930 19-OUTPUT DB1900Z LOW-POWER DERIVATIVE Pin Configuration 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 DIF 12 VDDA 1 54 GNDA 2 53 DIF 12 VDDIO 100M 133M 3 52 GND HIBW BYPM LOBW 4 51 DIF 11 CKPWRGD PD 5 50 DIF 11 GND 6 49 DIF 10 VDDR 7 48 DIF 10 DIF IN 8 47 DIF IN 9 46 GND 9ZXL1930 VDD SMB A0 tri 10 45 DIF 9 SMBDAT 11 44 DIF 9 SMBCLK 12 43 DIF 8 SMB A1 tri 13 42 FBOUT NC 14 41 DIF 8 VDDIO FBOUT NC 15 40 GND GND 16 39 DIF 7 DIF 0 17 38 DIF 7 DIF 0 18 37 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Power Management Table Inputs Outputs Control Bits PLL State DIF IN/ SMBus DIF x/ FBOUT NC/ CKPWRGD PD DIF IN EN bit DIF x FB OUT NC 0 X X Low/Low Low/Low OFF 0 Low/Low Running ON 1 Running 1 Running Running ON Power Connections PLL Operating Mode Table Pin Number HiBW BypM LoBW Byte0, bit (7:6) Description VDD VDDIO GND Low ( PLL Low BW) 00 Mid (Bypass) 01 1 2 Analog PLL 7 6 Analog Input High (PLL High BW) 11 16, 22, 27, 34, NOTE: PLL is off in Bypass mode 21, 33, 40, 28, 45, 64 DIF clocks 39, 46, 51, 58, 52, 57, 69 63, 70 Tri-Level Input Thresholds Level Voltage Functionality at Power-up (PLL mode) Low <0.8V DIF IN DIFx Mid 1.2<Vin<1.8V 100M 133M (MHz) (MHz) High Vin > 2.2V 1 100.00 DIF IN 0 133.33 DIF IN IDT 19-OUTPUT DB1900Z LOW-POWER DERIVATIVE 2 9ZXL1930 REV D 112015 DIF 18 DIF 18 GND VDDIO DIF 17 DIF 17 DIF 16 DIF 16 VDD GND DIF 15 DIF 15 DIF 14 DIF 14 GND VDDIO DIF 13 DIF 13