IDT5T9950/A 2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR. INDUSTRIAL TEMPERATURE RANGE 2.5V PROGRAMMABLE IDT5T9950/A SKEW PLL CLOCK DRIVER TURBOCLOCK II JR. FEATURES: DESCRIPTION: Ref input is 3.3V tolerant The IDT5T9950 is a high fanout 2.5V PLL based clock driver intended 4 pairs of programmable skew outputs for high performance computing and data-communications applications. A Low skew: 185ps same pair, 250ps all outputs key feature of the programmable skew is the ability of outputs to lead or lag Selectable positive or negative edge synchronization: the REF input signal. The IDT5T9950 has eight programmable skew Excellent for DSP applications outputs in four banks of 2. Skew is controlled by 3-level input signals that Synchronous output enable may be hard-wired to appropriate high-mid-low levels. Input frequency: When the sOE pin is held low, all the outputs are synchronously enabled. Std: 6MHz to 160MHz However, if sOE is held high, all the outputs except 2Q0 and 2Q1 are A: 6MHz to 200MHz synchronously disabled. The LOCK output asserts to indicate when Phase Output frequency: Lock has been achieved. Std: 6MHz to 160MHz Furthermore, when PE is held high, all the outputs are synchronized with A: 6MHz to 200MHz the positive edge of the REF clock input. When PE is held low, all the outputs 2x, 4x, 1/2, and 1/4 outputs are synchronized with the negative edge of REF. The IDT5T9950 has 3-level inputs for skew and PLL range control LVTTL outputs with 12mA balanced drive outputs. PLL bypass for DC testing External feedback, internal loop filter 12mA balanced drive outputs Low Jitter: <100ps cycle-to-cycle Standard and A speed grades Available in TQFP package FUNCTIONAL BLOCK DIAGRAM sOE 1Q0 Skew Select 1Q1 3 3 1F1:0 PE TEST 2Q0 Skew Select 3 2Q1 3 3 REF PLL 2F1:0 FB 3Q0 Skew 3 Select 3Q1 3 3 FS 3F1:0 4Q0 Skew Select 4Q1 3 3 4F1:0 The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE OCTOBER 2008 1 c 2002 Integrated Device Technology, Inc. DSC 5869/6IDT5T9950/A 2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR. INDUSTRIAL TEMPERATURE RANGE (1) PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Symbol Description Max Unit VDDQ, VDD Supply Voltage to Ground 0.5 to +4.6 V VI DC Input Voltage 0.5 to VDD+0.5 V REF Input Voltage 0.5 to +4.6 V 32 31 30 29 28 27 26 25 Maximum Power TA = 85C 0.7 W 3F1 1 24 1F1 Dissipation TA = 55C 1.1 4F0 2 23 1F0 TSTG Storage Temperature Range 65 to +150 C 22 4F1 3 sOE NOTE: 1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause PE VDDQ 21 4 permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the VDDQ 5 20 1Q0 operational sections of this specification is not implied. Exposure to absolute- maximum-rated conditions for extended periods may affect device reliability. 4Q1 6 19 1Q1 4Q0 7 18 GND CAPACITANCE(TA = +25C, f = 1MHz, VIN = 0V) 17 GND GND 8 Parameter Description Typ. Max. Unit 9 10 11 12 13 14 15 16 CIN Input Capacitance 5 7 pF NOTE: 1. Capacitance applies to all inputs except TEST, FS, nF 1:0 , and DS 1:0 . TQFP TOP VIEW PIN DESCRIPTION Pin Name Type Description REF I N Reference Clock Input FB I N Feedback Input (1) TEST I N When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew Selections (See Control Summary Table) remain in effect. Set LOW for normal operation. (1) sOE I N Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q0 and 2Q1) in a LOW state (for PE = H) - 2Q0 and 2Q1 may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and sOE is HIGH, the nF 1:0 pins act as output disable controls for individual banks when nF 1:0 = LL. Set sOE LOW for normal operation (has internal pull-down). P E I N Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference clock (has internal pull-up). nF 1:0 I N 3-level inputs for selecting 1 of 9 skew taps or frequency functions FS I N Selects appropriate oscillator circuit based on anticipated frequency range. (See Programmable Skew Range.) nQ 1:0 OUT Four banks of two outputs with programmable skew VDDQ PWR Power supply for output buffers VDD PWR Power supply for phase locked loop, lock output, and other internal circuitry GND PWR Ground NOTE: 1. When TEST = MID and sOE = HIGH, PLL remains active with nF 1:0 = LL functioning as an output disable control for individual output banks. Skew selections remain in effect unless nF 1:0 = LL. 2 GND 3F0 3Q1 FS 3Q0 VDD VDDQ REF FB GND VDDQ TEST 2Q1 2F1 2Q0 2F0