Product Information

5T9304PGG

5T9304PGG electronic component of Renesas

Datasheet
Clock Buffer 450 MHz 2.5V LVDS 1:4 Clock Buffer

Manufacturer: Renesas
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 10.3801 ea
Line Total: USD 10.3801

0 - Global Stock
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
0 - Global Stock


Ships to you between Thu. 11 Apr to Mon. 15 Apr

MOQ : 1
Multiples : 1

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5T9304PGG
Renesas

1 : USD 8.4686
10 : USD 7.4205
25 : USD 7.2111
100 : USD 6.3272
248 : USD 6.1411
558 : USD 5.6642
1054 : USD 5.3385

     
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RoHS - XON
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Propagation Delay - Max
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Q4 A1 LVDS, 1:4 Clock Buffer Terabuffer 5T9304 DATA SHEET General Description Features The 5T9304 differential clock buffer has a user-selectable differential Guaranteed low skew: 50ps (maximum) input to four LVDS outputs. The fanout from a differential input to four Very low duty cycle distortion: 125ps (maximum) LVDS outputs reduces loading on the preceding driver and provides Propagation delay: 1.75ns (maximum) an efficient clock distribution network. The 5T9304 can act as a Up to 450MHz operation translator from a differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A Selectable inputs single-ended 3.3V / 2.5V LVTTL input can also be used to translate Hot insertable and over-voltage tolerant inputs to LVDS outputs. The redundant input capability allows for an 3.3V/2.5V LVTTL, HSTL eHSTL, LVEPECL (2.5V), asynchronous change-over from a primary clock source to a LVPECL (3.3V), CML or LVDS input interface secondary clock source. Selectable reference inputs are controlled Selectable differential inputs to four LVDS outputs by SEL. 2.5V V DD The 5T9304 outputs can be asynchronously enabled/disabled. 0C to 70C ambient operating temperature When disabled, the outputs will drive to the value selected by the GL pin. Multiple power and grounds reduce noise. Available in lead-free (RoHS 6) package Applications Clock distribution Pin Assignment GND A2 1 24 2 23 A2 PD GND RESERVED 3 22 4 21 V V DD DD 5 20 Q3 Q1 6 19 Q3 Q1 Q2 Q4 7 18 Q2 8 17 V V DD 9 16 DD SEL GL 10 15 G 11 14 A1 GND 12 13 5T9304 24-Lead TSSOP 4.4mm x 7.8mm x 1.0mm package body G Package Top View 5T9304 Rev A 5/13/15 1 2015 Integrated Device Technology, Inc.5T9304 DATA SHEET Block Diagram GL G Q1 OUTPUT CONTROL Q1 PD Q2 OUTPUT CONTROL Q2 A1 1 A1 Q3 OUTPUT CONTROL Q3 A2 Q4 OUTPUT 0 CONTROL A2 Q4 SEL LVDS, 1:4 CLOCK BUFFER TERABUFFER 2 Rev A 5/13/15

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
CEL (RENESAS)
ID4
IDT
IDT, Integrated Device Technology Inc
INTEGRATED DEVICE
INTEGRATED DEVICE TECHNOLOGY
INTEGRATED DEVICES TECH AID
Intersil
INTERSIL - FGC
Intersil(Renes as Electronics)
Intersil(Renesas Electronics)
ITS
REA
RENESAS
RENESAS (IDT)
RENESAS (INTERSIL)
Renesas / IDT
Renesas / Intersil
Renesas Electronics
Renesas Electronics America
RENESAS TECHNOLOGY

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