Programmable Clock Generator 5P49V5925 DATASHEET Description Features The 5P49V5925 is a programmable clock generator intended Generates up to four independent output frequencies for high-performance consumer, networking, industrial, High-performance, low phase noise PLL, < 0.7 ps RMS computing, and data-communications applications. typical phase jitter on outputs Configurations may be stored in on-chip One-Time 2 Four fractional output dividers (FODs) Programmable (OTP) memory or changed using I C interface. This is IDTs fifth generation of programmable clock Independent Spread Spectrum capability on each output technology (VersaClock 5). Four banks of internal non-volatile in-system programmable or factory programmable OTP memory The frequencies are generated from a single reference clock. 2 The reference clock can come from one of the two redundant I C serial programming interface clock inputs. A glitchless manual switchover function allows Five LVCMOS outputs, including one reference output one of the redundant clocks to be selected during normal I/O Standards: operation. Single-ended I/Os: 1.8V to 3.3V LVCMOS Two select pins allow up to 4 different configurations to be programmed and accessible using processor GPIOs or Input frequency ranges: bootstrapping. The different selections may be used for LVCMOS Reference Clock Input (XIN/REF) 1MHz to different operating modes (full function, partial function, partial 200MHz power-down), regional standards (US, Japan, Europe) or LVDS, LVPECL, HCSL Differential Clock Input (CLKIN, system production margin testing. CLKINB) 1MHz to 200MHz 2 The device may be configured to use one of two I C Crystal frequency range: 8MHz to 40MHz addresses to allow multiple devices to be used in a system. Output frequency ranges: LVCMOS Clock Outputs 1MHz to 200MHz Pin Assignment Individually selectable output voltage (1.8V, 2.5V, 3.3V) for each output Redundant clock inputs with manual switchover Programmable loop bandwidth Programmable slew rate control Programmable crystal load capacitance Individual output enable/disable Power-down mode 24 23 22 21 20 19 1 V 2 18 DDO CLKIN 1.8V, 2.5V or 3.3V core V , V DDD DDA 2 17 OUT2 CLKINB Available in 24-pin VFQFPN 4mm x 4mm package XOUT 3 16 NC EPAD -40 to +85C industrial temperature operation GND 4 XIN/REF 15 V 3 DDO 5 14 V OUT3 DDA 6 13 NC CLKSEL 8 9 10 11 12 7 24-pin VFQFPN 5P49V5925 FEBRUARY 21, 2019 1 2019 Integrated Device Technology, Inc. SD/OE OUT0 SEL I2CB V 0 SEL1/SDA DDO SEL0/SCL V DDD V 4 V 1 DDO DDO OUT4 OUT1 NC NC5P49V5925 DATASHEET Functional Block Diagram V 0 DDO XIN/REF OUT0 SEL I2CB XOUT V 1 DDO OUT1 FOD1 CLKIN V 2 DDO CLKINB OUT2 FOD2 CLKSEL PLL V 3 DDO SD/OE OUT3 FOD3 SEL1/SDA 4 V DDO OTP and SEL0/SCL Control Logic OUT4 FOD4 V DDA V DDD Applications Ethernet switch/router PCI Express 1.0/2.0/3.0 Broadcast video/audio timing Multi-function printer Processor and FPGA clocking Any-frequency clock conversion MSAN/DSLAM/PON Fiber Channel, SAN Telecom line cards 1 GbE and 10 GbE PROGRAMMABLE CLOCK GENERATOR 2 FEBRUARY 21, 2019