DATASHEET PECL/CMOS TO CMOS CLOCK DRIVER ICS558-01 Description Features The ICS558-01 accepts a high speed input of either PECL 16-pin TSSOP package or CMOS, integrates a divider of 1, 2, 3, or 4, and provides Pb (lead) free package four CMOS low skew outputs. The chip also has output Selectable PECL or CMOS inputs enables so that one, three, or all four outputs can be Operates up to 250 MHz tri-stated. Works as a voltage translator The ICS558-01 is a member of the IDT Clock Blocks family Four low skew (<250 ps) outputs of clock generation, synchronization, and distribution Selectable internal divider devices. Operating input voltages of 3.3 V or 5.0 V Operating output voltages of 2.5 V, 3.3 V or 5.0 V Ideal for IA64 designs Block Diagram OE0 VDDP VDDC PECLIN CLK1 PECLIN CLK2 1 Output Divide CMOSIN 0 CLK3 SELPECL CLK4 2 S0, S1 OE1 GND GND IDT / ICS PECL/CMOS TO CMOS CLOCK DRIVER 1 ICS558-01 REV F 051310ICS558-01 PECL/CMOS TO CMOS CLOCK DRIVER PECL CLOCK DRIVER Input Clock Selection Pin Assignment SELPECL Input S0 1 16 SELPECL 0CMOSIN S1 2 15 VDDC 1 PECLIN VDDP 3 14 CLK1 PECLIN 4 13 CLK2 Tri-State Table PECLIN 5 12 CLK3 OE1 OE0 CLK 1 CLK 2, 3, 4 GND 6 11 CLK4 0 0 Tri-state Tri-state CMOSIN 7 10 GND 0 1 Clock ON Tri-state OE0 8 9 OE1 1 0 Tri-state Clock ON 1 1 Clock ON Clock ON 16-pin 173 Mil (0.65mm) TSSOP Output Divide Selection S1 S0 Output Divide 00 /1 01 /2 10 /3 11 /4 Pin Descriptions Pin Pin Pin Type Pin Description Number Name 1 S0 Input Select 0 for output divider. See table above. Internal pull-up to VDDP. 2 S1 Input Select 1 for output divider. See table above. Internal pull-up to VDDP. 3 VDDP Power Connect to +3.3 V or +5 V. Decouple to pin 6. 4 PECLIN Clock Input PECL input. Connect to ground if not used. 5 PECLIN Clock Input Complimentary PECL input. Connect to ground if not used. 6 GND Power Connect to ground. 7 CMOSIN Clock Input CMOS input. Connect to ground if not used. 8 OE0 Input Output Enable 0. See table above. Internal pull-up to VDDP. 9 OE1 Input Output Enable 1. See table above. Internal pull-up to VDDP. 10 GND Power Connect to ground. 11 CLK4 Output Low skew clock output. 12 CLK3 Output Low skew clock output. 13 CLK2 Output Low skew clock output. 14 CLK1 Output Low skew clock output. 15 VDDC Power Connect to +2.5 V, +3.3 V, or +5 V. Decouple to pin 10. 16 SELPECL Input Selects PECL or CMOS input. See table above. Internal pull-up to VDDP. IDT / ICS PECL/CMOS TO CMOS CLOCK DRIVER 2 ICS558-01 REV F 051310