MB85RS64TPNF-G-JNERE2

FUJITSU SEMICONDUCTOR DATA SHEET DS501-00051-2v0-E Memory FRAM 64 K (8 K 8) Bit SPI MB85RS64T DESCRIPTION MB85RS64T is a FRAM (Ferroelectric Random Access Memory) chip in a configuration of 8,192 words 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile memory cells. MB85RS64T adopts the Serial Peripheral Interface (SPI). The MB85RS64T is able to retain data without using a back-up battery, as is needed for SRAM. 13 The memory cells used in the MB85RS64T can be used for 10 read/write operations, which is a significant 2 improvement over the number of read and write operations supported by Flash memory and E PROM. 2 MB85RS64T does not take long time to write data like Flash memories or E PROM, and MB85RS64T takes no wait time. FEATURES Bit configuration : 8,192 words 8 bits Serial Peripheral Interface : SPI (Serial Peripheral Interface) Correspondent to SPI mode 0 (0, 0) and mode 3 (1, 1) Operating frequency : 10 MHz (Max) 13 High endurance : 10 times / byte Data retention : 10 years ( 85 C) Operating power supply voltage : 1.8 V to 3.6 V Low power consumption : Operating power supply current 0.8 mA (Max 10 MHz) Standby current 9 A (Typ) Operation ambient temperature range : 40 C to +85 C Package : 8-pin plastic SOP (FPT-8P-M02) 8-pin plastic SON (LLC-8P-M04) RoHS compliant Copyright 2018FUJITSU SEMICONDUCTOR LIMITED 2018.07MB85RS64T PIN ASSIGNMENT (TOP VIEW) (TOP VIEW) CS 1 8 VDD 1 8 VDD CS HOLD SO 2 7 2 7 SO HOLD DIE PAD SCK 3 6 WP WP 3 6 SCK 4 5 VSS SI VSS 4 5 SI (LCC-8P-M04) (FPT-8P-M02) PIN FUNCTIONAL DESCRIPTIONS Pin Pin No. Functional description Name Chip Select pin This is an input pin to make chip select. When CS is the H level, device is in deselect 1CS (standby) status and SO becomes High-Z. Inputs from other pins are ignored at this time. When CS is the L level, device is in select (active) status. CS has to be the L level before inputting op-code. Write Protect pin This is a pin to control writing to a status register. The writing of status register (see 3WP STATUS REGISTER) is protected in related with WP and WPEN. See WRITING PROTECT for detail. Hold pin This pin is used to interrupt serial input/output without making chip deselect. When 7HOLD HOLD is the L level, hold operation is activated, SO becomes High-Z, and SCK and SI become dont care. While the hold operation, CS shall be retained the L level. Serial Clock pin 6SCK This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising edge, SO is output synchronously to a falling edge. Serial Data Input pin 5SI This is an input pin of serial data. This inputs op-code, address, and writing data. Serial Data Output pin 2SO This is an output pin of serial data. Reading data of FRAM memory cell array and status register are output. This is High-Z during standby. 8 VDD Supply Voltage pin 4 VSS Ground pin It is allowed for the DIE PAD on the bottom of the SON8 package to be floating (no con- DIE PAD nection to anything) or to be connected to VSS. 2 DS501-00051-2v0-E