Product Information

MPC875VR133

MPC875VR133 electronic component of NXP

Datasheet
Microprocessors - MPU 133 MHz 176 MIPS

Manufacturer: NXP
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)
N/A

Obsolete
Availability Price Quantity
0 - Global Stock

MOQ : 1
Multiples : 1
1 : USD 51.0822
10 : USD 47.6553
25 : USD 45.6581
100 : USD 41.3776
N/A

Obsolete
0 - Global Stock

MOQ : 1
Multiples : 1
1 : USD 33.6609
N/A

Obsolete
0 - Global Stock

MOQ : 300
Multiples : 300
300 : USD 32.0864
N/A

Obsolete
0 - Global Stock

MOQ : 1
Multiples : 1
1 : USD 40.068
10 : USD 37.3788
25 : USD 37.2924
50 : USD 36.3636
100 : USD 34.7544
250 : USD 34.2468
500 : USD 34.2468
1000 : USD 33.9444
2500 : USD 32.9184
N/A

Obsolete
     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Series
Core
Data Bus Width
Maximum Clock Frequency
Interface Type
Operating Supply Voltage
Number of Cores
Mounting Style
Package / Case
L1 Cache Instruction Memory
L1 Cache Data Memory
Minimum Operating Temperature
Maximum Operating Temperature
Packaging
Brand
Data Ram Size
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Program Memory Size
I/O Voltage
Processor Series
Factory Pack Quantity :
Tradename
Memory Type
Cnhts
Hts Code
Mxhts
Number Of Timers/Counters
Watchdog Timers
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Document Number: MPC875EC Freescale Semiconductor Rev. 4, 08/2007 Technical Data MPC875/MPC870 PowerQUICC Hardware Specifications Contents This hardware specification contains detailed information on 1. Overview . 2 power considerations, DC/AC electrical characteristics, and 2. Features 2 AC timing specifications for the MPC875/MPC870. The 3. Maximum Tolerated Ratings . 9 CPU on the MPC875/MPC870 is a 32-bit core built on 4. Thermal Characteristics 10 5. Power Dissipation . 11 Power Architecture technology that incorporates memory 6. DC Characteristics 11 management units (MMUs) and instruction and data caches. 7. Thermal Calculation and Measurement 12 For functional characteristics of the MPC875/MPC870, refer 8. Power Supply and Power Sequencing . 14 9. Mandatory Reset Configurations . 15 to the MPC885 PowerQUICC Family Reference Manual. 10. Layout Practices 16 To locate published errata or updates for this document, refer 11. Bus Signal Timing 17 12. IEEE 1149.1 Electrical Specifications . 45 to the MPC875/MPC870 product summary page on our 13. CPM Electrical Characteristics . 47 website listed on the back cover of this document or, contact 14. USB Electrical Characteristics . 67 your local Freescale sales office. 15. FEC Electrical Characteristics . 67 16. Mechanical Data and Ordering Information . 71 17. Document Revision History . 80 Freescale Semiconductor, Inc., 20032007. All rights reserved.Overview 1Overview The MPC875/MPC870 is a versatile single-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications and communications and networking systems. The MPC875/MPC870 provides enhanced ATM functionality over that of other ATM-enabled members of the MPC860 family. Table 1 shows the functionality supported by the MPC875/MPC870. Table 1. MPC875/MPC870 Devices Cache (Kbytes) Ethernet Security Part SCC SMC USB Engine I Cache D Cache 10BaseT 10/100 MPC875 8812 1 1 1 Yes MPC870 8 8 2 1 1 No 2Features The MPC875/MPC870 is comprised of three modules that each use the 32-bit internal bus: a MPC8xx core, a system integration unit (SIU), and a communications processor module (CPM). The following list summarizes the key MPC875/MPC870 features: Embedded MPC8xx core up to 133 MHz Maximum frequency operation of the external bus is 80 MHz (in 1:1 mode) The 133-MHz core frequency supports 2:1 mode only The 66-/80-MHz core frequencies support both the 1:1 and 2:1 modes Single-issue, 32-bit core (compatible with the Power Architecture definition) with thirty-two 32-bit general-purpose registers (GPRs) The core performs branch prediction with conditional prefetch and without conditional execution 8-Kbyte data cache and 8-Kbyte instruction cache (see Table 1) Instruction cache is two-way, set-associative with 256 sets in 2 blocks Data cache is two-way, set-associative with 256 sets Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache blocks Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and are lockable on a cache block basis MMUs with 32-entry TLB, fully associative instruction and data TLBs MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes 16 virtual address spaces and 16 protection groups Advanced on-chip emulation debug mode Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits) MPC875/MPC870 PowerQUICC Hardware Specifications, Rev. 4 2 Freescale Semiconductor

Tariff Desc

8542.31.00 52 No ..CMOS and MOS Microprocessors (MPU), Microcontrollers (MCU) and Digital Signal Processors (DSP)

Electronic integrated circuits: Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Monolithic integrated circuits Digital.
FR9
Freescale
FREESCALE SEMI
Freescale Semicon
FREESCALE SEMICONDUC
Freescale Semiconductor
Freescale Semiconductor - NXP
NXP
NXP Freescale
NXP (FREESCALE)
NXP / Freescale
NXP SEMI
NXP Semicon
NXP SEMICONDUCTOR
NXP Semiconductors
NXP USA Inc.
PH3
PHI

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