Product Information

MR10Q010CSC

MR10Q010CSC electronic component of Everspin

Datasheet
Memory; MRAM; QPI, QUAD SPI, SPI; 128kx8bit; 1Mbit; SO16; 3÷3.6VDC

Manufacturer: Everspin
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 10.998 ea
Line Total: USD 10.998

873 - Global Stock
Ships to you between
Wed. 10 Apr to Fri. 12 Apr
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
835 - Global Stock


Ships to you between Wed. 10 Apr to Fri. 12 Apr

MOQ : 1
Multiples : 1

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MR10Q010CSC
Everspin

1 : USD 9.729
10 : USD 9.1655
25 : USD 8.2225
100 : USD 7.7625
250 : USD 7.659
480 : USD 7.59
2880 : USD 7.59

     
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MR10Q010 1 Mb High Speed Quad SPI MRAM FEATURES High bandwidth Read and Write at 52MB/sec Quad I/O with the use of dual purpose pins to maintain a low pin count RoHS Operates in both standard, single SPI mode and high speed quad SPI mode Fast quad Read and Write with quad address input and quad I/O Intended for next generation RAID controllers, server system logs, storage device buffers, and embedded system data and program memory Data is non-volatile with retention greater than 20 years Automatic data protection on power loss 16-SOIC Unlimited write endurance Low-current sleep mode Dual 3.3v V / 1.8v V power supply DD DDQ Tamper Detect function will detect possible data modification from outside mag- netic fields. Quad Peripheral Interface (QPI) mode is supported to enhance system performance 24-BGA for Execute in Place (XIP) operation. MSL Level 3. DESCRIPTION The MR10Q010 is the ideal memory solution for applications that must store and retrieve data and programs quickly using a small number of pins, low power, and choice of a 24-ball BGA or a 16-pin SOIC package. The four I/Os in Quad SPI mode allow very fast reads and writes, making it an attractive alternative to conventional parallel data bus inter- faces in next generation RAID controllers, server system logs, storage device buffers, and embedded system data and program memory. Using Everspins patented MRAM technology, both reads and writes can occur randomly in memory with no delay between writes. Standard Serial Peripheral Interface (SPI), Quad SPI and Quad Peripheral Interface (QPI) modes are supported at a clock rate up to 104MHz. XIP operation is supported for Read commands in all three modes. The MR10Q010 Quad SPI MRAM is organized as 131,072 words of 8 bits. Operational Overview Mode Command Set Utility Commands XIP Command Operation Write Enable/Disable, Sleep Mode, Read/Write Read 40MHz. Write, Fast Read SPI Mode Status Register, Tamper Detect, Read Device ID, Fast Read 104MHz Enable QPI Mode Quad I/O mode Read/Write data, Fast Read Quad Output, Fast Read Quad SPI Mode None. or both address and data Quad Address and Data Enables command instruction Fast Read, Fast Read Quad Output, QPI Mode Disable QPI Mode. entry in quad I/O mode. (2 clocks) Fast Read Quad Address and Data Copyright 2018 Everspin Technologies, Inc. 1 MR10Q010 Revision 5.6, 6/2018MR10Q010 TABLE OF CONTENTS Operational Overview ....................................................................................................................1 OVERVIEW ............................................................................................................................................7 Table 1 Operational Parameters Summary ...................................................................................................... 7 Operation in 3.3v Data Bus Systems - Evaluation Board Available .............................................7 Figure 1 MR10Q010 Block Diagram .................................................................................................................... 8 Figure 2 System Configuration ............................................................................................................................. 9 Figure 3 16-SOIC Package Pin Assignments ..................................................................................................10 Table 2 16-SOIC Pin Functions ............................................................................................................................10 Figure 4 24-BGA Package Ball Assignments ..................................................................................................12 Table 3 24-BGA Ball Functions ............................................................................................................................12 STATUS REGISTER ............................................................................................................................. 14 Table 4 Status Register Bit Definitions ............................................................................................................. 14 Memory Protection Modes .......................................................................................................... 15 Table 5 Memory Protection Modes ..................................................................................................................15 Block Protection Modes ............................................................................................................... 15 Table 6 Block Memory Write Protection ..........................................................................................................15 SPI COMMUNICATIONS PROTOCOL ................................................................................................ 16 SPI MODE COMMANDS .................................................................................................................... 16 Table 7 SPI Mode Commands Overview .........................................................................................................17 SPI Mode Commands Overview .................................................................................................. 17 Read Status Register (RDSR) ........................................................................................................ 18 Figure 5 Read Status Register (RDSR) Command Operation ..................................................................18 Write Enable (WREN) .................................................................................................................... 19 Figure 6 Write Enable (WREN) Command Operation ................................................................................19 Write Disable (WRDI) .................................................................................................................... 20 Figure 7 Write Disable (WRDI) Command Operation ................................................................................20 Copyright 2018 Everspin Technologies, Inc. 2 MR10Q010 Revision 5.6, 6/2018

Tariff Desc

8542.32.00 33 No ..Memory cards (other than "smart" cards and SIMM), which incorporate E2PROM, SRAM, DRAM or flash memory (for example, for PCMCIA applications)
Everspin Tech
Everspin Technologies

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