ESMT M13S2561616A (2S) DDR SDRAM 4M x 16 Bit x 4 Banks Double Data Rate SDRAM Features Double-data-rate architecture, two data transfers per clock cycle Bi-directional data strobe (DQS) Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition Four bank operation CAS Latency : 2.5, 3, 4 Burst Type : Sequential and Interleave Burst Length : 2, 4, 8 All inputs except data & DM are sampled at the rising edge of the system clock (CLK) Data I/O transitions on both edges of data strobe (DQS) DQS is edge-aligned with data for READs center-aligned with data for WRITEs Data mask (DM) for write masking only V = 2.5V 0.2V, V = 2.5V 0.2V DD DDQ 7.8us refresh interval Auto & Self refresh 2.5V I/O (SSTL 2 compatible) Ordering Information Product ID Max Freq. V Package Comments DD M13S2561616A -5TG2S 200MHz (DDR400) 66 pin TSOPII M13S2561616A -6TG2S 166MHz (DDR333) 2.5V Pb-free M13S2561616A -5BG2S 200MHz (DDR400) 60 Ball BGA M13S2561616A -6BG2S 166MHz (DDR333) Elite Semiconductor Memory Technology Inc. Publication Date : Apr. 2014 Revision : 1.0 1/49 ESMT M13S2561616A (2S) Functional Block Diagram CLK Clock Bank D CLK Generator Bank C CKE Bank B Address, BA Row Address Buffer Mode Register & Bank A & Extended Mode Register Refresh Counter DM DQS Sense Amplifier Column CS Column Decoder Address Buffer RAS & Refresh CAS Counter Data Control Circuit DQ WE DLL CLK, CLK Elite Semiconductor Memory Technology Inc. Publication Date : Apr. 2014 Revision : 1.0 2/49 Command Decoder Control Logic Row Decoder Latch Circuit Input & Output Buffer