Product Information

M12L2561616A-6TG2T

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Datasheet
SDRAM TOSP-54 RoHS
Manufacturer: ESMT



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Manufacturer
ESMT
Product Category
SRAM
Category
Sram
Rohs
Y
Package
TOSP - 54
Brand Category
Esmt
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ESMT M12L2561616A (2S) SDRAM 4M x 16 Bit x 4 Banks Synchronous DRAM FEATURES ORDERING INFORMATION y JEDEC standard 3.3V power supply Product ID Max Freq. Package Comments y LVTTL compatible with multiplexed address y Four banks operation M12L2561616A-5TG2S 200MHz TSOP II Pb-free y MRS cycle with address key programs M12L2561616A-6TG2S 166MHz TSOP II Pb-free - CAS Latency ( 2 & 3 ) - Burst Length ( 1, 2, 4, 8 & full page ) M12L2561616A-7TG2S 143MHz TSOP II Pb-free - Burst Type ( Sequential & Interleave ) M12L2561616A-5BG2S 200MHz BGA Pb-free y All inputs are sampled at the positive going edge of the system clock M12L2561616A-6BG2S 166MHz BGA Pb-free y Burst Read single write operation M12L2561616A-7BG2S 143MHz BGA Pb-free y DQM for masking y Auto & self refresh y 64ms refresh period (8K cycle) y All Pb-free products are RoHS-Compliant GENERAL DESCRIPTION The M12L2561616A is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 16 bits. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. PIN CONFIGURATION (TOP VIEW) BALL CONFIGURATION (TOP VIEW) (TSOPII 54L, 400milX875mil Body, 0.8mm Pin Pitch) (BGA54, 8mmX8mmX1mm Body, 0.8mm Ball Pitch) 54 VSS VDD 1 DQ0 2 53 DQ15 12 345 6 7 8 9 52 VDDQ 3 VSSQ 4 51 DQ14 DQ1 A VSS DQ15 VSSQ VDDQ DQ0 VDD 50 DQ2 5 DQ13 6 49 VDDQ VSSQ 48 DQ3 7 DQ12 B VSSQ DQ2 DQ1 DQ14 DQ13 VDDQ 8 47 DQ11 DQ4 VDDQ 9 46 VSSQ DQ12 DQ11 VSSQ VDDQ DQ4 DQ3 C 45 DQ10 DQ5 10 DQ6 11 44 DQ9 D VDDQ VSSQ DQ6 43 DQ10 DQ9 DQ5 VSSQ 12 VDDQ 13 42 DQ8 DQ7 41 VDD 14 VSS E DQ8 NC VSS VDD LDQM DQ7 15 40 NC LDQM WE 16 39 UDQM F UDQM CLK CKE CAS RAS WE 38 CLK CAS 17 RAS 18 37 CKE BA0 G A12 A11 A9 BA1 CS 36 A12 CS 19 BA0 20 35 A11 34 A9 BA1 21 H A8 A0 A10 A7 A6 A1 22 33 A8 A10/AP 32 A0 23 A7 VSS A5 A4 A3 A2 VDD J 24 31 A6 A1 A2 25 30 A5 29 A4 A3 26 VDD 27 28 VSS Elite Semiconductor Memory Technology Inc. Publication Date: Feb. 2015 Revision: 1.4 1/45 ESMT M12L2561616A (2S) BLOCK DIAGRAM CLK Clock Generator Bank D CKE Bank C Bank B Row Address Address Buffer Mode Bank A & Register Refresh Counter Sense Amplifier L(U)DQM Column CS Column Decoder Address RAS Buffer CAS & Counter Data Control Circuit DQ WE PIN DESCRIPTION PIN NAME INPUT FUNCTION CLK System Clock Active on the positive going edge to sample all inputs Disables or enables device operation by masking or enabling all Chip Select inputs except CLK , CKE and L(U)DQM CS Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior new command. CKE Clock Enable Disable input buffers for power down in standby. Row / column address are multiplexed on the same pins. A0 ~ A12 Address Row address : RA0~RA12, column address : CA0~CA8 Selects bank to be activated during row address latch time. BA1, BA0 Bank Select Address Selects bank for read / write during column address latch time. Latches row addresses on the positive going edge of the CLK with Row Address Strobe RAS RAS low. (Enables row access & precharge.) Latches column address on the positive going edge of the CLK with Column Address Strobe CAS CAS low. (Enables column access.) Enables write operation and row precharge. Write Enable WE Latches data in starting from CAS , WE active. Makes data output Hi-Z, t after the clock and masks the output. SHZ L(U)DQM Data Input / Output Mask Blocks data input when L(U)DQM active. DQ0 ~ DQ15 Data Input / Output Data inputs / outputs are multiplexed on the same pins. V / V Power Supply / Ground Power and ground for the input buffers and the core logic. DD SS Isolated power supply and ground for the output buffers to provide V / V Data Output Power / Ground DDQ SSQ improved noise immunity. NC No Connection This pin is recommended to be left No Connection on the device. Elite Semiconductor Memory Technology Inc. Publication Date: Feb. 2015 Revision: 1.4 2/45 Command Decoder Control Logic Row Decoder Latch Circuit Input & Output Buffer

Tariff Desc

8542.32.00 31 No ..Random Access Memory (RAM) including Single Inline Memory Modules (SIMMS), Dual Inline Memory Modules (DIMMS), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SD RAM), Rambus Dynamic Random Access Memory (RD RAM) and other similar memory
ESMT
ESMT(Elite Semicon Memory Tech)