PI6C10810 1.2V-2.5V, 250MHz, 1:10 Networking Clock Buffer Features Description High-speed, low-noise, non-inverting split 1-10 buffer T h e P I 6 C 1 0 8 1 0 i s a 1 . 2 V t o 2 . 5 V h i g h - s p e e d , l o w - n o i s e Maximum Frequency up to 250 MHz 1-10 non-inverting clock buffer. The key goal in designing the PI6C10810 is to target networking applications that require low- Low output skew < 60ps (Bank A, 2.5V) skew, low-jitter, and high-frequency clock distribution. Low duty cycle distortion < 200ps Providing output-to-output skew as low as 60ps, the PI6C10810 Low propagation delay < 2.0ns (2.5V) is an ideal clock distribution device for synchronous systems. Choice of 1.2V, 1.5V, 1.8V or 2.5V supply voltage on Bank A, Designing synchronous networking systems requires a tight level Bank B, Bank C of skew from a large number of outputs. Industrial temperature range: 40C to 85C CLK0-4 operate from V supply. DDA Packages (Pb-free & Green): 20-pin, TSSOP (L20) CLK5-6 operate from V supply. DDC 20-pin, SSOP (H20) CLK7-9 operate from V supply. DDB 20-pin, QSOP (Q20) Block Diagram Pin Configuration V DDA CLK0 BUF IN V 1 20 DDB CLK1 GND CLK9 2 19 BUF IN CLK0 CLK8 3 18 CLK2 V GND DDA 4 17 CLK1 CLK7 16 5 CLK3 GND V 6 15 DDC CLK2 7 14 CLK6 CLK4 V DDA GND 8 13 CLK3 CLK5 9 12 CLK5 GND CLK4 10 11 CLK6 CLK7 Pin Description Pin Name Description CLK8 BUF IN Input CLK 0:9 Outputs CLK9 GND Ground V , V , V Power (1.2V, 1.5V, 1.8V, 2.5V) DDA DDB DDC V V DDC DDB PS9014A 02/23/11 11-0015 1PI6C10810 1.2V-2.5V, 250MHz, 1:10 Networking Clock Buffer 2.5V Absolute Maximum Ratings (Above which the useful life may be impaired. For user guidelines only, not tested.) Note: S t r e s s e s g r e a t e r t h a n t h o s e l i s t e d u n d e r M A X I - Storage Temperature ........................................................... 65C to +150C M U M R AT I N G S m a y c a u s e p e r m a n e n t d a m a g e t o t h e device. This is a stress rating only and functional operation V Voltage .......................................................................... 0.5V to +3.6V DD of the device at these or any other conditions above those Output Voltage (max. 3.6V) .......................................... 0.5V to V +0.5V DD indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions Input Voltage (max 3.6V) .............................................. 0.5V to V +0.5V DD for extended periods may affect reliability. 2.5V DC Characteristics (Over Operating Range: V V V = 2.5V 0.2V, T = -40 to 85C) DDA, DDB, DDC A (1) (2) Parameters Description Test Conditions Min. Typ. Max. Units V Supply Voltage 2.3 2.5 2.7 DD V Input HIGH Voltage Logic HIGH level 1.7 3.6 IH V V Input LOW Voltage Logic LOW level -0.3 0.7 IL I Input Current V = Max, Vin = V or GND I pin 15 A I DD DD I = -1mA 2.0 OH V Output High Voltage V = Min., V = V or V I = -2mA 1.7 OH DD IN IH IL OH I = -8mA 1.7 OH V I = 1mA 0.1 OL V Output LOW Voltage V = Min., V - V or V I = 2mA 0.2 OL DD IN IH IL OL I = 8mA 0.2 OL Notes: 1. For Max. or Min. conditions, use appropriate operating range values. 2. Typical values are at V = 2.5V, +25C ambient and maximum loading. DD 2.5V AC Characteristics (Over Operating Range: V V V = 2.5V 0.2V, T = -40 to 85C) DDA, DDB, DDC A (1) Parameters Description Min. Typ Max. Units Test Conditions F Input Frequency 0 250 MHz IN (2) t t Propagation Delay BUF IN to CLKn 1.0 1.5 2.0 PLH, PHL Output to Output Skew Bank A (CLK0 - CLK4) 60 60 between any two outputs (3) t SK(O) Bank C (CLK5 - CLK6) 30 30 of the same device Bank B (CLK7 - CLK9) R = 500-Ohm, C = 150 same transition 150 L L ps 3pF, 125 MHz Out- Pulse Skew between opposite transitions (3) t 100 200 SK(P) puts are measured (t -t ) of the same output PHL PLH V /2 DD Part to Part Skew between two identical outputs of dif- (3)(5) t 300 SK(T) (4) ferent parts on the same board t Duty Cycle In Ins edge rate 45 55 dc in % t Duty Cycle Out 40 57.5 dc out (5) t Additive Jitter 50 ps j t Output Rise Time 20%-80% CLKn 0.5 0.7 R(O) R = 500-Ohm, C = L L ns 3pF t Output Fall Time 80%-20% CLKn 0.5 0.7 F(O) Notes: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew measured at worst case temperature (max. temp). 4. Identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade. 5. Guaranteed by design. PS9014A 02/23/11 2 11-0015