CY96610 Series 2 F MC-16FX,16-bit Proprietary Microcontroller 2 CY96610 series is based on Cypress advanced F MC-16FX architecture (16-bit with instruction pipeline for RISC-like 2 performance). The CPU uses the same instruction set as the established F MC-16LX family thus allowing for easy 2 2 2 migration of F MC-16LX Software to the new F MC-16FX products. F MC-16FX product improvements compared to the previous generation include significantly improved performance - even at the same operation frequency, reduced power consumption and faster start-up time.For high processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 32MHz operation frequency from an external 4MHz to 8MHz resonator. The result is a minimum instruction cycle time of 31.2ns going together with excellent EMI behavior. The emitted power is minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree allows selecting suitable operation frequencies for peripheral resources independent of the CPU speed. Features Technology Low Voltage Detection Function 0.18m CMOS Reset is generated when supply voltage falls below programmable reference voltage CPU Code Security 2 F MC-16FX CPU Protects Flash Memory content from unintended read-out Optimized instruction set for controller applications (bit, byte, word and long-word data types, 23 different DMA addressing modes, barrel shift, variety of pointers) Automatic transfer function independent of CPU, can be 8-byte instruction queue assigned freely to resources Signed multiply (16-bit 16-bit) and divide (32-bit/16-bit) instructions available Interrupts Fast Interrupt processing System Clock 8 programmable priority levels On-chip PLL clock multiplier ( 1 to 8, 1 when PLL stop) Non-Maskable Interrupt (NMI) 4MHz to 8MHz crystal oscillator (maximum frequency when using ceramic resonator CAN depends on Q-factor) Supports CAN protocol version 2.0 part A and B Up to 8MHz external clock for devices with fast clock input feature ISO16845 certified 32.768kHz subsystem quartz clock Bit rates up to 1Mbps 100kHz/2MHz internal RC clock for quick and safe startup, 32 message objects clock stop detection function, watchdog Each message object has its own identifier mask Clock source selectable from mainclock oscillator, subclock Programmable FIFO mode (concatenation of message oscillator and on-chip RC oscillator, independently for CPU objects) and 2 clock domains of peripherals Maskable interrupt The subclock oscillator is enabled by the Boot ROM program controlled by a configuration marker after a Power Disabled Automatic Retransmission mode for Time or External reset Triggered CAN applications Low Power Consumption - 13 operating modes (different Programmable loop-back mode for self-test operation Run, Sleep, Timer, Stop modes) USART On-Chip Voltage Regulator Full duplex USARTs (SCI/LIN) Internal voltage regulator supports a wide MCU supply Wide range of baud rate settings using a dedicated reload voltage range (Min=2.7V), offering low power consumption timer Special synchronous options for adapting to different synchronous serial protocols Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-04709 Rev.*D Revised November 30, 2017 CY96610 Series LIN functionality working either as master or slave LIN Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral device clock as counter clock or of selected Reload timer underflow as clock input Extended support for LIN-Protocol to reduce interrupt load Can be triggered by software or reload timer A/D Converter Can trigger ADC conversion SAR-type Timing point capture 8/10-bit resolution Quadrature Position/Revolution Counter (QPRC) Signals interrupt on conversion end, single conversion mode, continuous conversion mode, Up/down count mode, Phase difference count mode, Count stop conversion mode, activation by software, external mode with direction trigger, reload timers and PPGs 16-bit position counter Range Comparator Function 16-bit revolution counter Two 16-bit compare registers with interrupt Source Clock Timers Detection edge of the three external event input pins AIN, Three independent clock timers (23-bit RC clock timer, 23- BIN and ZIN is configurable bit Main clock timer, 17-bit Sub clock timer) Real Time Clock Hardware Watchdog Timer Operational on main oscillation (4MHz), sub oscillation Hardware watchdog timer is active after reset (32kHz) or RC oscillation (100kHz/2MHz) Window function of Watchdog Timer is used to select the Capable to correct oscillation deviation of Sub clock or RC lower window limit of the watchdog interval oscillator clock (clock calibration) Reload Timers Read/write accessible second/minute/hour registers 16-bit wide Can signal interrupts every half second/second/minute/hour/day 1 2 3 4 5 6 Prescaler with 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 of peripheral clock frequency Internal clock divider and prescaler provide exact 1s clock Event count function External Interrupts Free-Running Timers Edge or Level sensitive Signals an interrupt on overflow, supports timer clear upon Interrupt mask bit per channel match with Output Compare (0, 4) Each available CAN channel RX has an external interrupt 1 2 3 4 5 6 7 8 Prescaler with 1, 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 for wake-up of peripheral clock frequency Selected USART channels SIN have an external interrupt for wake-up Input Capture Units 16-bit wide Non Maskable Interrupt Signals an interrupt upon external event Disabled after reset, can be enabled by Boot-ROM depending on ROM configuration block Rising edge, Falling edge or Both (rising & falling) edges sensitive Once enabled, can not be disabled other than by reset High or Low level sensitive Output Compare Units Pin shared with external interrupt 0 16-bit wide Signals an interrupt when a match with Free-running Timer I/O Ports occurs Most of the external pins can be used as general purpose A pair of compare registers can be used to generate an I/O output signal All push-pull outputs Bit-wise programmable as input/output or peripheral signal Programmable Pulse Generator Bit-wise programmable input enable 16-bit down counter, cycle and duty setting registers One input level per GPIO-pin (either Automotive or CMOS Can be used as 2 8-bit PPG hysteresis) Interrupt at trigger, counter borrow and/or duty match Bit-wise programmable pull-up resistor PWM operation and one-shot operation Document Number: 002-04709 Rev.*D Page 2 of 64