AN59389 Host Sourced Serial Programming for CY8C20xx6A, CY8C20xx6AS, CY8C20xx6L and CY8C20xx7/S Author: Chris Hammer Associated Project: Yes Associated Part Family: CY8C20xx6A, CY8C20xx6AS CY8C20xx6L and CY8C20xx7 Software Version: PSoC Designer 5.4 CP1 Related Documents: ISSP Programming Specifications Host Sourced Serial Programming (HSSP) is a method of in-circuit serial programming (using ISSP protocol) of the CY8C20xx6A, CY8C20xx6AS, CY8C20xx6L and CY8C20xx7 devices from an onboard host processor. AN59389 explains how to use and port the HSSP code example, provided along with this application note, to the desired host processor for programming the CY8C20xx6A, CY8C20xx6AS, CY8C20xx6L and CY8C20xx7 devices. preferred programming mode, is used only when the Introduction system is powered externally. In this case, the XRES pin on the target PSoC is toggled at the end of the process to Cypresss PSoC microcontrollers are easy-to-use, flexible, bring it out of programming mode and resume normal and have a cost-effective mix of reprogrammable analog operation. In the Power Cycle mode, the host and digital resources. These features provide many microcontroller switches the PSoCs power on and off. opportunities for creative designs, one of which is programming the PSoC serially by an on-board host In each programming mode, the host needs three I/O pins. processor. This method is used to install or update These are: serial data (SDATA), serial clock (SCLK), and firmware in-field or even completely reprogram the PSoC external reset (XRES) in the Reset mode, and SDATA, for a different function. SCLK, and PSoC power (PWR) in the Power Cycle mode. The software influences these pins. Cypress created the HSSP Code Example to give system designers a starting point to create their own serial The SDATA pin on the host processor must be programming software. Designers have to make minimal bidirectional. The host must be able to change the modifications to the code to make it compatible with their properties of this pin so that it drives a signal to the PSoC, specific host programmer. The Code Example covers only is released to High-Z state, and is read. the CY8C20xx6A, CY8C20xx6AS, CY8C20xx6L, and CY8C20xx7 devices and provides a high level of abstraction. For more information on serial programming, refer to ISSP Programming Specifications. This application note describes the implementation on a high level. Protocol details and meaning of the vectors are proprietary and intentionally omitted. Overview The HSSP Code Example has four major parts: main function, sub functions for various programming steps, low-level I/O functions, and definition files. The system designer s direct involvement with the code is to set certain properties through defines to provide code to fill a 128-byte buffer with programming data and to provide low-level drivers for the host I/O. PSoC devices are programmed in two different modes: Reset and Power Cycle. Reset mode, which is the www.cypress.com Document No. 001-59389 Rev. *G 1 Host Sourced Serial Programming for CY8C20xx6A, CY8C20xx6AS, CY8C20xx6L and CY8C20xx7/S fSDATACheck() SCLKHigh() Property Selection SCLKLow() SetSCLKStrong() The designer must set two properties: Label and SetSDATAHigh() Description. To do this, comment or uncomment certain SetSDATALow() defines in the ISSP DIRECTIVES.H file. These SetSDATAHiZ() SetSDATAStrong() defines are clearly marked withUser Attention SetXRESStrong() Require and are easy to find. You can also do a page AssertXRES() search for individual labels. An explanation for each DeassertXRES() property and its label follows. SetSCLKHiZ() Property: Programming mode SetTargetVDDStrong() Label: PROGRAMMING MODE ApplyTargetVDD() Description: Comment out this define if you use RemoveTargetVDD() the power cycle mode. Uncommenting the define causes the target to be programmed in reset mode. Loading Data into RAM Buffer Property: Target PSoC Device Label: TARGET PSOC The HSSP code takes data from a 128-byte buffer to Description: Select the target CY8C20xx6, or program PSoC flash blocks sequentially. This process CY8C20xx7 PSoC in this section. Only one device is starts at the lowest block address. After the first block is enabled at any given time and every other device is programmed, the same buffer is used to program further commented out. flash blocks. The designer must provide a code to fill this buffer Low-Level Driver Modifications depending on the data source (USB, RS-232, SD Card, The designer gives host-specific code to manipulate the and so on). There are two functions to be written for the pins involved in programming the target PSoC. These specific host processor usedLoadProgramData() and APIs are markedProcessor Specifi andUser Attention fLoadSecurityData(). These functions are found in Require and are found in ISSP DRIVER ROUTINES.C. ISSP DRIVER ROUTINES.C and are marked with Processor Specifi andUser Attention Required In Port Bit Masks: There are four port bit masks that their original state, these functions call two secondary must be adjusted for the specific host processor being functions that load the buffer with pseudo test data for used. Note that though there are four bits to set, only debugging purposes. In the final version, delete or three are used in programming, depending on the comment out these calls. choice of programming method SDATA, SCLK, and XRES in reset mode SDATA, SCLK, and PWR in Modifying Flash Block Sequence or power cycle mode. Quantity Delay(n) Function: This function is adjusted so that In some cases you have to program a specific area in each iteration of the while loop takes at least 1 s. flash. An example is an area set aside for characterization, Generally, there is no upper limit for the loop time. calibration, or firmware field upgrades. These features are However, the longer this loop takes, the longer it takes usually implemented using the EEPROM user module. to program the target. For example, if the host However, in some cases programming them directly into microcontroller is also a PSoC, each iteration takes the PSoC saves code space if that is a limitation. about 1 s and there is a 3-s overhead. Therefore, You can change the start address of the target block and the function generates a delay of the order in which the blocks are programmed. This does n+3 s, where n is the parameter passed to the not cause any problems as each programming sequence function. To adjust the delay time for your host includes the block address. However, remember the processor, modify the defines in ISSP DELAYS.H. following points: Port Bit Manipulation Functions: These functions If the programming loop is modified, the same manipulate host pins to generate signals needed to changes must be applied to the verify loop to avoid program the PSoC. They deal with driving pins high verification failure. and low and releasing pins to High-Z state. A list of these functions follows. Most of the functions are self The code accumulates the checksum as it goes. It explanatory, but they are all documented within the examines the checksum against the entire flash up to code. The descriptions are also available in the that point. If you program only a section of flash, set Appendix. the variable iChecksumData accordingly. www.cypress.com Document No. 001-59389 Rev. *G 2