Product Information

CY7C1615KV18-300BZXI

CY7C1615KV18-300BZXI electronic component of Infineon

Datasheet
SRAM 144Mb 1.8V 300Mhz 4M x 36 QDR II SRAM

Manufacturer: Infineon
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 302.2761 ea
Line Total: USD 302.2761

0 - Global Stock
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
0 - Global Stock


Ships to you between Fri. 05 Apr to Thu. 11 Apr

MOQ : 105
Multiples : 105
105 : USD 706.8865

0 - Global Stock


Ships to you between Fri. 05 Apr to Thu. 11 Apr

MOQ : 1
Multiples : 1
1 : USD 302.2761
10 : USD 296.0221
25 : USD 289.7681
50 : USD 283.5141
100 : USD 277.2602
500 : USD 271.0062

0 - Global Stock


Ships to you between Thu. 11 Apr to Mon. 15 Apr

MOQ : 105
Multiples : 105
105 : USD 323.689

     
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CY7C1613KV18/CY7C1615KV18 144-Mbit QDR II SRAM Four-Word Burst Architecture 144-Mbit QDR II SRAM Four-Word Burst Architecture Features Configuration Separate independent read and write data ports CY7C1613KV18 8 M 18 Supports concurrent transactions CY7C1615KV18 4 M 36 333 MHz clock for high bandwidth Functional Description Four-word burst for reducing address bus frequency The CY7C1613KV18, and CY7C1615KV18 are 1.8-V Double Data Rate (DDR) interfaces on both read and write ports synchronous pipelined SRAMs, equipped with QDR II (data transferred at 666 MHz) at 333 MHz architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The Two input clocks (K and K) for precise DDR timing read port has dedicated data outputs to support read operations SRAM uses rising edges only and the write port has dedicated data inputs to support write Two input clocks for output data (C and C) to minimize clock operations. QDR II architecture has separate data inputs and skew and flight time mismatches data outputs to completely eliminate the need to turn around the data bus that exists with common I/O devices. Each port can Echo clocks (CQ and CQ) simplify data capture in high speed be accessed through a common address bus. Addresses for systems read and write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the QDR II read and write Single multiplexed address input bus latches address inputs ports are completely independent of one another. To maximize for read and write ports data throughput, both read and write ports are equipped with Separate port selects for depth expansion DDR interfaces. Each address location is associated with four 18-bit words (CY7C1613KV18), or 36-bit words Synchronous internally self-timed writes (CY7C1615KV18) that burst sequentially into or out of the Quad data rate (QDR ) II operates with 1.5-cycle read latency device. Because data can be transferred into and out of the when DOFF is asserted high device on every rising edge of both input clocks (K and K and C and C), memory bandwidth is maximized while simplifying Operates similar to a QDR I device with one-cycle read latency system design by eliminating bus turnarounds. when DOFF is asserted low Depth expansion is accomplished with port selects, which Available in 18, and 36 configurations enables each port to operate independently. Full data coherency, providing most current data All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output Core V = 1.8 V (0.1 V) I/O V = 1.4 V to V DD DDQ DD registers controlled by the C or C (or K or K in a single clock Supports both 1.5 V and 1.8 V I/O supply domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Available in 165-ball fine-pitch ball grid array (FBGA) package (15 17 1.4 mm) For a complete list of related documentation, click here. Offered in both Pb-free and non Pb-free packages Variable drive high-speed transceiver logic (HSTL) output buffers JTAG 1149.1 compatible test access port (TAP) Phase Locked Loop (PLL) for accurate data placement Selection Guide Description 333 MHz 300 MHz 250 MHz Unit Maximum operating frequency 333 300 250 MHz Maximum operating current 18 760 710 Not Offered mA 36 1010 950 830 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-44273 Rev. *L Revised January 2, 20182M x 18 Array 1M x 36 Array 2M x 18 Array 1M x 36 Array 2M x 18 Array 1M x 36 Array 2M x 18 Array 1M x 36 Array CY7C1613KV18/CY7C1615KV18 Logic Block Diagram CY7C1613KV18 18 D 17:0 Write Write Write Write 21 Address A Reg Reg Reg Reg (20:0) Register 21 Address A (20:0) Register RPS K Control CLK K Logic C Gen. DOFF Read Data Reg. C CQ 72 V 36 REF 18 CQ Reg. Reg. Control 18 WPS Logic 18 18 36 Q BWS Reg. 1:0 17:0 18 Logic Block Diagram CY7C1615KV18 36 D 35:0 Write Write Write Write 20 Address A Reg Reg Reg Reg (19:0) Register 20 Address A (19:0) Register RPS K Control CLK K Logic Gen. C DOFF Read Data Reg. C CQ 144 V 72 REF 36 CQ Reg. Reg. Control WPS 36 Logic 36 36 72 BWS Q 3:0 Reg. 35:0 36 Document Number: 001-44273 Rev. *L Page 2 of 32 Write Add. Decode Write Add. Decode Read Add. Decode Read Add. Decode

Tariff Desc

8542.32.00 31 No ..Random Access Memory (RAM) including Single Inline Memory Modules (SIMMS), Dual Inline Memory Modules (DIMMS), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SD RAM), Rambus Dynamic Random Access Memory (RD RAM) and other similar memory
CYP
Cypress
Cypress / Spansion
CYPRESS SEMI
Cypress Semicon
Cypress Semiconductor
Cypress Semiconductor Corp
INF
INFINEON
Infineon IR
INFINEON (CYPRESS)
Infineon (IRF)
Infineon / Cypress
Infineon / IR
INFINEON TECH ICs
Infineon Technologies
INFINEON TECHNOLOGIES AG
Infineon Technologies Americas Corp.
Infinite Power Solutions
INTERNATIONAL RECTIF
INTERNATIONAL RECTIFIER
International Rectifier HiRel Products
INTL RECTIFIER
IR
IRH
Ramtron
Ramtron / Cypress Semiconductor
Ramtron International Corp
SP9
SPANSION

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